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參數(shù)資料
| 型號(hào)： | TMX320C6211BGLW167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 1/83頁(yè) |
| 文件大小： | 1176K |
| 代理商： | TMX320C6211BGLW167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Excellent Price/Performance Digital Signal
Processors (DSPs): TMS320C62x
(TMS320C6211 and TMS320C6211B)
Eight 32-Bit Instructions/Cycle
C6211, C6211B, C6711, and C6711B are
Pin-Compatible
150-, 167-MHz Clock Rates
6.7-, 6-ns Instruction Cycle Time
1200, 1333 MIPS
Extended Temperature Device (C6211B)
VelociTI
Advanced Very Long Instruction
Word (VLIW) C62x
DSP Core (C6211/11B)
Eight Highly Independent Functional
Units:
Six ALUs (32-/40-Bit)
Two 16-Bit Multipliers (32-Bit Results)
Load-Store Architecture With 32 32-Bit
General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Byte-Addressable (8-, 16-, 32-Bit Data)
8-Bit Overflow Protection
Saturation
Bit-Field Extract, Set, Clear
Bit-Counting
Normalization
L1/L2 Memory Architecture
32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
Device Configuration
Boot Mode: HPI, 8-, 16-, and 32-Bit ROM
Boot
Endianness: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
Glueless Interface to Asynchronous
Memories: SRAM and EPROM
Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
512M-Byte Total Addressable External
Memory Space
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
Direct Interface to T1/E1, MVIP, SCSA
Framers
ST-Bus-Switching Compatible
Up to 256 Channels Each
AC97-Compatible
Serial-Peripheral-Interface (SPI)
Compatible (Motorola
)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG
)
Boundary-Scan-Compatible
256-Pin Ball Grid Array (BGA) Package
(GFN Suffix)
0.18-
μ
m/5-Level Metal Process
CMOS Technology
3.3-V I/Os, 1.8-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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