欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào): TMX320C6211GDP167
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 67/83頁(yè)
文件大小: 1176K
代理商: TMX320C6211GDP167
TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
67
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP
(see Figure 37)
NO.
150
167
UNIT
MIN
2P
§
MAX
2
3
t
c(CKRX)
t
w(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
ns
ns
0.5t
c(CKRX)
1
5
t
su(FRH-CKRL)
Setup time external FSR high before CLKR low
Setup time, external FSR high before CLKR low
20
1
6
3
22
3
3
4
23
1
6
3
ns
6
t
h(CKRL-FRH)
Hold time external FSR high after CLKR low
Hold time, external FSR high after CLKR low
ns
7
t
su(DRV-CKRL)
Setup time DR valid before CLKR low
Setup time, DR valid before CLKR low
ns
8
t
h(CKRL-DRV)
Hold time DR valid after CLKR low
Hold time, DR valid after CLKR low
ns
10
t
su(FXH-CKXL)
Setup time external FSX high before CLKX low
Setup time, external FSX high before CLKX low
ns
11
t
h(CKXL-FXH)
Hold time external FSX high after CLKX low
Hold time, external FSX high after CLKX low
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
§
The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP
and other device is 83 Mbps for 167 MHz CPU clock or 75 Mbps for 150 MHz CPU clock; where the McBSP is either the master or the slave.
Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP
communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever
value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 30 ns as the minimum CLKR/X clock cycle (by setting the appropriate
CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock
cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with
CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY =
01b or 10b) and the other device the McBSP communicates to is a slave.
相關(guān)PDF資料
PDF描述
TMX320C6211GGP167 FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMP320C6211GGP167 FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMJ320C6211GGP167 FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMX320C6201GGP167 FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMP320C6211GJC167 TRIMMER, 1K
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMX320C6211GFN 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PORCESSORS
TMX320C6211GFN167 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMX320C6211GFN21 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PORCESSORS
TMX320C6211GGP100 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMX320C6211GGP167 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS
主站蜘蛛池模板: 日土县| 沈阳市| 平凉市| 阿合奇县| 华亭县| 铁力市| 芮城县| 朝阳市| 特克斯县| 共和县| 增城市| 伊川县| 上虞市| 桐柏县| 德保县| 定远县| 芮城县| 白城市| 涪陵区| 乌兰浩特市| 永胜县| 锡林浩特市| 凌云县| 上蔡县| 萨嘎县| 恩施市| 喀喇沁旗| 赤水市| 三穗县| 马鞍山市| 延寿县| 禹州市| 清水县| 庄河市| 龙岩市| 泽普县| 英山县| 武鸣县| 万载县| 商洛市| 图们市|