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參數(shù)資料
| 型號： | TMX320C6413ZTS400 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 87/140頁 |
| 文件大小： | 1958K |
| 代理商： | TMX320C6413ZTS400 |
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IEEE 1149.1 JTAG Compatibility Statement
87
April 2004
Revised May 2005
SPRS247E
4.10
IEEE 1149.1 JTAG Compatibility Statement
The TMS320C6413/C6410 DSP requires that both TRST and RESET be asserted upon power up to be
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both
resets are required for proper operation.
Note: TRST is synchronous and
must
be clocked by TCLK; otherwise, BSCAN may not respond as expected
after TRST is asserted.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a
JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be
released in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan
instructions work correctly independent of current state of RESET.
For maximum reliability, the TMS320C6413/C6410 DSP includes an internal pulldown (IPD) on the TRST pin
to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always
be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When
using this type of JTAG controller, assert TRST to intialize the DSP after powerup and externally drive TRST
high before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must occur to latch the state of EMU1 and
EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Normal/Emulation mode.
For more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN_WARNING section of the TMS320C6413/C6410 BSDL file contains information and
constraints regarding proper device operation while in Boundary Scan Mode.
For more detailed information on the C6413/C6410 JTAG emulation, see the
TMS320C6000 DSP Designing
for JTAG Emulation Reference Guide
(literature number SPRU641).
4.11
EMIF Device Speed
The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the
following requirements:
1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
up to 1 CE space of buffers connected to EMIF
EMIF trace lengths between 1 and 3 inches
143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.
Verification of AC timings is mandatory when using configurations other than those specified above. TI
recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the
Using IBIS Models
for Timing Analysis
application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
For more detailed information on the C6413/C6410 EMIF peripheral, see the
TMS320C6000 DSP External
Memory Interface (EMIF) Reference Guide
(literature number SPRU266).
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相關代理商/技術參數(shù) |
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