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參數資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發送器為622.08，麻省理工學院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數： | 1/54頁 |
| 文件大小： | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Termination/Generation of 155.52-Mbit/s or
622.08-Mbit/s SONET/SDH Frames Carrying
ATM Cells; Including:
– Frame Scrambling/Descrambling
– Pointer Processing
– ATM-Cell Delineation
– ATM-Cell Extraction/Insertion
– ATM-Cell Payload
Scrambling/Descrambling
– Cell-Rate Decoupling
Access to Receive and Transmit
Transport-Overhead (TOH) and
Path-Overhead (POH) Bytes Through the
Controller Interface
Detects Multiple-Bit Errors and Corrects
Single-Bit Errors in the 5-Byte ATM
Headers of Incoming ATM Cells
Separate Serial Receive- and Transmit-Data
Communication Ports Allow Access to Data
Communications and Orderwire-Overhead
Bytes
Alarm Generation/Checking in Accordance
With BellCore, ANSI, and ITU-T
Specifications
Performance Monitors/Counters Provide
Statistics on B1/B2/B3 Coding Violations,
B1/B2/B3 Block Errors, Line and Path
Far-End Block Errors (Line FEBEs and Path
FEBEs) and Other Status Data
Supports Boundary Scan Through a 5-Wire
JTAG Interface in Accordance With IEEE
Std 1149.1-1990 (Includes IEEE Std
1149.1a-1993) IEEE Standard Test-Access
Port and Boundary-Scan Architecture
description
The synchronous optical network (SONET)/synchronous digital hierarchy (SDH) asynchronous transport mode
(ATM) line-interface receiver/transmitter provides a versatile solution for transporting ATM cells over the
SONET/SDH network at 155.52 Mbit/s or 622.08 Mbit/s.
On the receive side, the TNETA1600 accepts byte-wide data aligned to proper SONET- /SDH-byte boundaries,
performs frame alignment and descrambling, and extracts SONET/SDH payload and overhead. The overhead
is placed in the receive-overhead RAM where each byte can be accessed through the controller interface. Cell
boundaries are established in the payload and ATM cells are extracted, descrambled, and passed to the receive
output FIFO for output to the ATM-layer device (i.e., a reassembly device).
On the transmit side, complete ATM cells are scrambled and placed in a SONET/SDH synchronous payload
envelope (SPE). Transport- and path- overhead bytes are programmable through the transmit-overhead RAM.
The overhead and payload are scrambled and sent out as a byte-wide data stream.
The TNETA1600 is characterized for operation over a temperature range of –40
°
C to 85
°
C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright
1996, Texas Instruments Incorporated
P
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