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參數資料
| 型號： | TP3054 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | Codec |
| 英文描述： | “Enhanced” Serial Interface CMOS CODEC/Filter(加強型串行接口CMOS編解碼器/濾波器) |
| 中文描述： | “增強”串行接口的CMOS編解碼器/過濾器（加強型串行接口的CMOS編解碼器/濾波器） |
| 文件頁數： | 4/16頁 |
| 文件大小： | 250K |
| 代理商： | TP3054 |
Functional Description
(Continued)
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
seeFigure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the encoder sample-and-hold circuit.
The A/D is of companding type according to
m
-law
(TP3054) or A-law (TP3057) coding conventions. A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (t
MAX
) of nominally 2.5V peak (see
table of Transmission Characteristics). The FS
X
frame sync
pulse controls the sampling of the filter output, and then the
successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out through D
X
at the next FS
X
pulse. The total encoding delay will be ap-
proximately 165
m
s (due to the transmit filter) plus 125
m
s
(due to encoding delay), which totals 290
m
s. Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration.
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3057) or
m
-law (TP3054) and the 5th order low pass filter corrects for
the sin x/x attenuation due to the 8 kHz sample/hold. The
filter is then followed by a 2nd order RC active post-filter/
power amplifer capable of driving a 600
X
load to a level of
7.2 dBm. The receive section is unity-gain. Upon the occur-
rence of FS
R
, the data at the D
R
input is clocked in on the
falling edge of the next eight BCLK
R
(BCLK
X
) periods. At
the end of the decoder time slot, the decoding cycle begins,
and 10
m
s later the decoder DAC output is updated. The
total decoder delay is
E
10
m
s (decoder update) plus
110
m
s (filter delay) plus 62.5
m
s (
(/2
frame), which gives
approximately 180
m
s.
4
相關PDF資料 |
PDF描述 |
|---|---|
| TP3056BDWR | PCM CODEC|SINGLE|CMOS|SOP|16PIN|PLASTIC |
| TP3056B | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3056BDW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3056BN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3098 | TRANSISTOR | BJT | NPN | 200MA I(C) | RFMOD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TP3054A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3054ADW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3054ADWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3054AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP3054AN | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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