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參數資料
| 型號： | TP3057J-1 |
| 英文描述： | Rocker Switch; Circuitry:DPDT; Switch Operation:On-On; Contact Current Max:16A; Switch Terminals:Quick Connect; Actuator Color:White; Leaded Process Compatible:Yes; Mounting Type:Panel RoHS Compliant: Yes |
| 中文描述： | A律編解碼器 |
| 文件頁數： | 3/16頁 |
| 文件大小： | 250K |
| 代理商： | TP3057J-1 |
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initializ-
es the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the D
X
and VF
R
O
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLK
R
/PDN pinand FS
X
and/or FS
R
pulses must be pres-
ent. Thus, 2 power-down control modes are available. The
first is to pull the MCLK
R
/PDN pin high; the alternative is to
hold both FS
X
and FS
R
inputs continuously lowDthe device
will power-down approximately 1 ms after the last FS
X
or
FS
R
pulse. Power-up will occur on the first FS
X
or FS
R
pulse. The TRI-STATE PCM data output, D
X
, will remain in
the high impedance state until the second FS
X
pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive di-
rections. In this mode, a clock must be applied to MCLK
X
and the MCLK
R
/PDN pin can be used as a power-down
control. A low level on MCLK
R
/PDN powers up the device
and a high level powers down the device. In either case,
MCLK
X
will be selected as the master clock for both the
transmit and receive circuits. A bit clock must also be ap-
plied to BCLK
X
and the BCLK
R
/CLKSEL can be used to
select the proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame.
With a fixed level on the BCLK
R
/CLKSEL pin, BCLK
X
will be
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLK
R
/
CLKSEL. In this synchronous mode, the bit clock, BCLK
X
,
may be from 64 kHz to 2.048 MHz, but must be synchro-
nous with MCLK
X
.
Each FS
X
pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled D
X
output on the positive edge of BCLK
X
. After 8
bit clock periods, the TRI-STATE D
X
output is returned to a
high impedance state. With an FS
R
pulse, PCM data is
latched via the D
R
input on the negative edge of BCLK
X
(or
BCLK
R
if running). FS
X
and FS
R
must be synchronous with
MCLK
X/R
.
TABLE I. Selection of Master Clock Frequencies
BCLK
R
/CLKSEL
Master Clock
Frequency Selected
TP3057
TP3054
Clocked
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
0
1.536 MHz or
1.544 MHz
2.048 MHz
1
1.536 MHz or
1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK
X
and MCLK
R
must be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis-
sion performance, however, MCLK
R
should be synchronous
with MCLK
X
, which is easily achieved by applying only static
logic levels to the MCLK
R
/PDN pin. This will automatically
connect MCLK
X
to all internal MCLK
R
functions (see Pin
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
FS
X
starts each encoding cycle and must be synchronous
with MCLK
X
and BCLK
X
. FS
R
starts each decoding cycle
and must be synchronous with BCLK
R
. BCLK
R
must be a
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLK
X
and BCLK
R
may operate from
64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FS
X
and FS
R
, must be one bit clock period long,
with timing relationships specified inFigure 2. With FS
X
high
during a falling edge of BCLK
X
, the next rising edge of
BCLK
X
enables the D
X
TRI-STATE output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge dis-
ables the D
X
output. With FS
R
high during a falling edge of
BCLK
R
(BCLK
X
in synchronous mode), the next falling edge
of BCLK
R
latches in the sign bit. The following seven falling
edges latch in the seven remaining bits. All four devices
may utilize the short frame sync pulse in synchronous or
asynchronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses,
FS
X
and FS
R
, must be three or more bit clock periods long,
with timing relationships specified inFigure 3. Based on the
transmit frame sync, FS
X
, the COMBO will sense whether
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a mini-
mum of 160 ns. The D
X
TRI-STATE output buffer is enabled
with the rising edge of FS
X
or the rising edge of BCLK
X
,
whichever comes later, and the first bit clocked out is the
sign bit. The following seven BCLK
X
rising edges clock out
the remaining seven bits. The D
X
output is disabled by the
falling BCLK
X
edge following the eighth rising edge, or by
FS
X
going low, whichever comes later. A rising edge on the
receive frame sync pulse, FS
R
, will cause the PCM data at
D
R
to be latched in on the next eight falling edges of BCLK
R
(BCLK
X
in synchronous mode). All four devices may utilize
the long frame sync pulse in synchronous or asynchronous
mode.
In applications where the LSB bit is used for signalling with
FS
R
two bit clock periods long, the decoder will interpret the
lost LSB as ‘‘
(/2
’’ to minimize noise and distortion.
3
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TP3057N | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3057N/NOPB | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3057N/NOPB | 制造商:Texas Instruments 功能描述:, Peak Reflow Compatible (260 C):Yes |
| TP3057V | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3057V/63 | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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