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參數資料
型號: TP3410J
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 數字傳輸電路
英文描述: TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver
中文描述: DATACOM, DIGITAL SLIC, CDIP28
封裝: CERAMIC, DIP-28
文件頁數: 1/32頁
文件大小: 436K
代理商: TP3410J
TL/H/9151
T
September 1994
TP3410 ISDN Basic Access
Echo-Cancelling 2B1Q U Transceiver
General Description
The TP3410 is a complete monolithic transceiver for ISDN
Basic Access data transmission at either end of the U inter-
face. Fully compatible with ANSI specification T1.601, it is
built on National’s advanced double-metal CMOS process,
and requires only a single
a
5V power supply. A total of
160 kbps full-duplex transmission on a single twisted-pair is
provided, with user-accessible channels including 2 ‘B’
channels, each at 64 kbps, 1 ‘D’ channel at 16 kbps, and an
additional 4 kbps for loop maintenance. 12 kbps of band-
width is reserved for framing. 2B1Q Line coding is used, in
which pairs of binary bits are coded into 1 of 4 quantum
levels for transmission at 80k symbols/sec (hence 2 Binary/
1 Quaternary). To meet the very demanding specifications
for
k
1 in 10e7 Bit Error Rate even on long loops with cross-
talk, the device includes 2 Adaptive Digital Signal Proces-
sors, 2 Digital Phase-locked Loops and a controller for auto-
matic activation.
The digital interface on the device can be programmed for
compatibility with either of two types of control interface for
chip control and access to all spare bits. In one mode a
Microwire serial control interface is used together with a
2B
a
D digital interface which is compatible with the Time-di-
vision Multiplexed format of PCM Combo devices and back-
planes. This mode allows independent time-slot assignment
for the 2 B channels and the D channel.
Alternatively, the GCI (General Circuit Interface) may be se-
lected, in which the 2B
a
D data is multiplexed together with
control, spare bits and loop maintenance data on 4 pins.
Features
Y
2 ‘B’
a
‘D’ channel 160 kbps transceiver for LT and NT
Y
Meets ANSI T1.601 U.S. Standard
Y
2B1Q line coding with scrambler/descrambler
Y
Range exceeds 18 kft of
Y
26 AWG
Y
l
70 dB adaptive echo-cancellation and equalization
Y
On-chip timing recovery, no precision external
components
Y
Direct connection to small line transformer
Y
Automatic activation controller
Y
Selectable digital interface formats:
D TDM with time-slot assigner up to 64 slots, plus
MICROWIRE
TM
control interface
D GCI (General Circuit Interface), or
D IDL (Inter-chip Digital Link)
Y
Backplane clock DPLL allows free-running XTAL
Y
Elastic data buffers meet Q.502 wander/jitter for Slave-
slave mode on PBX Trunk Cards and DLC
Y
EOC and spare bits access with automatic validation
Y
Block error counter
Y
6 loopback test modes
Y
Single
a
5V supply, 325 mW active power
Y
20 mW idle mode with line signal ‘‘wake-up’’ detector
Applications
Y
LT, NT-1, NT-2 Trunks, U-TE’s, Regenerators etc.
Y
Digital Loop Carrier
Y
POTS Pair-Gain Systems
Y
Easy Interface to:
D Line Card Backplanes
D ‘‘S’’ Interface Device
D Codec/Filter Combos
D LAPD Processor
D HDLC Controller
TP3420A
TP3054/7 and TP3075/6
MC68302, HPC16400
TP3451
Combo
é
and TRI-STATE
é
are registered trademarks of National Semiconductor Corporation.
MICROWIRE
TM
is a trademark of National Semiconductor Corporation.
The General Circuit Interface (G.C.I.) is an interface specification of the Group-of-Four Euro-
pean Telecommunications Companies.
Block Diagram
TL/H/9151–1
Note:
Pin names show Microwire mode.
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
相關PDF資料
PDF描述
TP3420AJ ISDN S/T Interface Device
TP3420A ISDN S/T Interface Device
TP3420AN ISDN S/T Interface Device
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TP3464 MICROWIRE⑩ Interface Device (MID)
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