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參數資料
| 型號： | TPA0112PWPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDSO24 |
| 封裝： | GREEN, PLASTIC, HTSSOP-24 |
| 文件頁數： | 23/34頁 |
| 文件大?。?/td> | 655K |
| 代理商： | TPA0112PWPRG4 |
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ABSOLUTE MAXIMUM RATINGS
TPA0112
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
BYPASS
11
Tap to voltage divider for internal mid-supply bias generator
GAIN0
2
I
Bit 0 of gain control
GAIN1
3
I
Bit 1 of gain control
1, 12, 13,
GND
Ground connection for circuitry. Connected to the thermal pad.
24
LHPIN
6
I
Left channel headphone input, selected when SE/BTL is held high
LIN
10
I
Common left input for fully differential input. AC ground for single-ended inputs.
LLINEIN
5
I
Left channel line input, selected when SE/BTL is held low
LOUT+
4
O
Left channel positive output in BTL mode and positive output in SE mode
LOUT–
9
O
Left channel negative output in BTL mode and high impedance in SE mode
The input for PC Beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak) square wave is
PC-BEEP
14
I
input to PC-BEEP or PCB ENABLE is high.
If this terminal is high, the detection circuitry for PC-BEEP is overridden and passes PC-BEEP
PCB ENABLE
17
I
through the amplifier, regardless of its amplitude. If PCB ENABLE is floating or low, the amplifier
continues to operate normally.
PVDD
7, 18
I
Power supply for output stage
RHPIN
20
I
Right channel headphone input, selected when SE/BTL is held high
RIN
8
I
Common right input for fully differential input. AC ground for single-ended inputs.
RLINEIN
23
I
Right channel line input, selected when SE/BTL is held low
ROUT+
21
O
Right channel positive output in BTL mode and positive output in SE mode
ROUT–
16
O
Right channel negative output in BTL mode and high-impedance in SE mode
SHUTDOWN
22
I
Places entire IC in shutdown mode when held low, except PC-BEEP remains active
Input MUX control input. When this terminal is held high, the LHPIN or RHPIN and SE output is
SE/BTL
15
I
selected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected.
Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest
VDD
19
I
performance.
Connect to ground. Must be soldered down in all applications to properly secure the device on the
Thermal pad
PC board.
over operating free-air temperature range (unless otherwise noted)(1)
VDD
Supply voltage
6 V
VI
Input voltage
–0.3 V to VDD +0.3 V
Continuous total power dissipation
Internally Limited (see Dissipation Rating
Table)
TA
Operating free-air temperature range
–40
°C to 85°C
TJ
Operating junction temperature range
–40
°C to 150°C
Tstg
Storage temperature range
–65
°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
(1)
Stresses beyond thoselisted under absolute maximum ratings may cause permanent damage to the device.These are stress ratings
only, and functional operation of the device at theseor any other conditions beyond those indicated under recommended
operatingconditions is not implied. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability.
3
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