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參數(shù)資料
| 型號(hào)： | TPA2054D4YZKT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 0.94 W, 2 CHANNEL, AUDIO AMPLIFIER, BGA25 |
| 封裝： | 2.61 X 2.61 MM, GREEN, DSBGA-25 |
| 文件頁(yè)數(shù)： | 5/28頁(yè) |
| 文件大小： | 949K |
| 代理商： | TPA2054D4YZKT |
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DETAILED DESCRIPTION
GENERAL I
2C OPERATION
SINGLE AND MULTI-BYTE TRANSFERS
www.ti.com ..................................................................................................................................................................................................... SLOS607 – APRIL 2009
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially one bit at a time. The address and data 8-bit bytes are transferred most
significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device
with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the
bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data
terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on
SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions bust occur within
the low time of the clock period. Figure 43 shows a typical sequence. The master generates the 7-bit slave
address and the read/write (R/W) bit to open communication with another device and then waits for an
acknowledge condition. The TPA2054D4 holds SDA low during the acknowledge clock period to indicate
acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals
via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus.
Figure 43. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. Figure 43 shows a generic data
transfer sequence.
The serial control interface supports both single-byte and multi-byte read/write operations for all registers. During
multi-byte reads, the TPA2054D4 responds with data, one byte at a time, starting at the register assigned
provided the master devices continue to acknowledge.
The TPA2054D4 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has occurred.
For I2C sequential write transactions, the register issued then serves as the starting point and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines how many registers are written to.
Copyright 2009, Texas Instruments Incorporated
13
Product Folder Link(s): TPA2054D4
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