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SLOS528C – JULY 2009 – REVISED AUGUST 2010
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
The TPA3110D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed
circuit board. The following suggestions will help to meet EMC requirements.
Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (220 F or greater) bulk power supply decoupling capacitors should
be placed near the TPA3110D2 on the PVCCL and PVCCR supplies. Local, high-frequency bypass
capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the
thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR
ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1mF and
1mF also of good quality to the PVCC connections at each end of the chip.
Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
Grounding—The AVCC (pin 7) decoupling capacitor should be grounded to analog ground (AGND). The
PVCC decoupling capacitors should connect to PGND. Analog ground and power ground should be
connected at the thermal pad, which should be used as a central ground connection or star ground for the
TPA3110D2.
Output filter—The ferrite EMI filter
(Figure 43) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter
(Figure 41 and
Figure 42) should be placed close to the outputs.
The capacitors used in both the ferrite and LC filters should be grounded to power ground.
Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46mm by 2.35mm. Seven rows of
solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application
Report
SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB
footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3110D2 Evaluation Module (TPA3110D2EVM) User Manual. Both the EVM
user manual and the thermal pad application report are available on the TI Web site at
http://www.ti.com.SPACER
REVISION HISTORY
Changes from Original (July 2009) to Revision A
Page
Changed Changed the Stereo Class-D Amplifier with BTL Output and Single-Ended Input illustration
Figure 37 -
Corrected the pin names. ...................................................................................................................................................
20Changed Changed the Stereo Class-D Amplifier with PBTL Output and Single-Ended Input illustration
Figure 38 -
Corrected the pin names. ...................................................................................................................................................
21Changes from Revision A (July 2009) to Revision B
Page
Added slew rate adjustment information .............................................................................................................................
16Added AVCC to Pin 7 of Figure 38 .....................................................................................................................................
21Changes from Revision B (July 2010) to Revision C
Page
Replaced the Dissiations Ratings table with the Thermal Information table ........................................................................
2Copyright 2009–2010, Texas Instruments Incorporated
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