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參數資料
| 型號： | TPA5051RSAT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC16 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, QFN-16 |
| 文件頁數： | 3/23頁 |
| 文件大小： | 812K |
| 代理商： | TPA5051RSAT |
www.ti.com
FRAME DELAY REGISTERS (0x06, 0x0E)
RJ PACKET LENGTH REGISTERS (0x07, 0x0F)
SLOS497A – JUNE 2006 – REVISED JULY 2006
Table 4. Audio Delay Registers (0x02–0x05, 0x0A–0x0D)(1)
D13
D12
D11–D2
D1
D0
FUNCTION
0
Left and Right audio is passed to output with no delay.
0
1
Left and Right audio is delayed by 1 sample (1/Fs = delay time)
1
Left and Right audio is delayed by 4095 samples (4095/Fs = delay time)
(1)
Default values are in bold.
This register can be used to specify delay in video frames instead of audio samples. When the MSB is set to 1,
the audio delay registers (0x01–0x04) are bypassed and the Frame Delay Register is used to set the delay
based on the frame rate (D6), audio sample rate (D5–D3), and number of frames to delay (D2–D0).
The total audio delay time is calculated by the following formula:
Audio Delay (in samples) = int [# Delay Frames
× (1/Frame Rate) × Audio Sample Rate]
If the result of the formula above is greater than the maximum number of delay samples (4095 for TPA5051),
then the value is limited to this maximum before passing to the delay block.
Table 5. Frame Delay Registers (0x06, 0x0E)(1)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Settings in this register are masked and audio delay is determined by
settings in the right/left audio delay registers.
1
Right/left audio delay registers are masked and delay is determined by settings in
this register.
0
Frame rate = 50 Hz
1
Frame rate = 59.94 Hz
0
Audio sample rate = 32 kHz
0
1
Audio sample rate = 44.1 kHz
0
1
0
Audio sample rate = 48 kHz
0
1
Audio sample rate = 88.2 kHz
1
0
Audio sample rate = 96 kHz
1
0
1
Audio sample rate = 176.4 kHz
1
0
Audio sample rate = 192 kHz
1
Audio sample rate = 192 kHz
0
Delay frames = 1
0
1
Delay frames = 2
1
Delay frames = 8
(1)
Default values are in bold.
This register is only used in right justified mode. The decimal value of bits [5:0] represents the width of the
useable data in a right justified audio stream. The number of BCLK transitions between LRCLK transitions must
be greater than or equal to the packet length selected in this register. The maximum packet length value is 24
bits. Any setting greater whose numerical value is greater than 24 bits is limited to the maximum 24 bits.
Table 6. RJ Package Length (0x07, 0x0F)(1)
D5
D4
D3
D2
D1
D0
FUNCTION
0
Packet length = 0 bits
0
1
Packet length = 1 bits
0
1
X
Packet length = 24 bits
(1)
Default values are in bold.
11
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TPA5051RSATG4 | 功能描述:音頻 DSP 4Ch Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TPA5052 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO DIGITAL AUDIO LIP-SYNC DELAY |
| TPA5052EVM | 功能描述:音頻 IC 開發工具 AUD DELAY DEVICE RoHS:否 制造商:Texas Instruments 產品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TPA5052RSAR | 功能描述:音頻 DSP St Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TPA5052RSARG4 | 功能描述:音頻 DSP St Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
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