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參數資料
| 型號： | TPS2340APFP |
| 英文描述： | SMPS Controller |
| 中文描述： | 開關電源控制器 |
| 文件頁數： | 6/20頁 |
| 文件大小： | 411K |
| 代理商： | TPS2340APFP |
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating temperature range (–40
°
C < T
A
< 85
°
C),
3 V
≤
V
I(IN)
≤
13 V (unless otherwise noted) (continued)
ENABLE, active low (TPS2330)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH(ENABLE)
VIL(ENABLE)
High-level input voltage, ENABLE
2
V
Low-level input voltage, ENABLE
0.8
V
RI(ENABLE)
Input pullup resistance,
ENABLE
See Note 3
100
200
300
k
td_off(ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) ncreasing above stop threshold; 100
ns rise time, 20 mV overdrive (see Note 2)
60
μ
s
td_on(ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) decreasing below start threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
125
μ
s
NOTES:
2. Specified, but not production tested.
3. Test IO of ENABLE at VI(ENABLE) = 1 V and 0 V, then RI(ENABLE) =
1 V
IO_0V
IO_1V
ENABLE, active high (TPS2331)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH(ENABLE)
VIL(ENABLE)
High-level input voltage, ENABLE
2
V
Low-level input voltage, ENABLE
0.7
V
RI(ENABLE)
Input pulldown resistance,
ENABLE
100
150
300
k
td_on(ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) increasing above start threshold;
100 ns rise time, 20 mV overdrive (see Note 2)
85
μ
s
td_off(ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) decreasing below stop threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
100
μ
s
NOTE 2: Specified, but not production tested.
PREREG
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREG
PREREG output voltage
4.5
≤
VI(IN)
≤
13 V
VI(IN) = 3 V
3.5
4.1
5.5
V
Vdrop_PREREG
PREREG dropout voltage
0.1
V
VREG UVLO
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOT(UVLOstart)
VOT(UVLOstop)
Vhys(UVLO)
Output threshold voltage, start
2.75
2.85
2.95
V
Output threshold voltage, stop
2.65
2.78
V
Hysteresis
50
75
mV
UVLO sink current, GATE
VI(GATE) = 2 V
10
mA
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