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參數資料
| 型號： | TPS2491DGSG4 |
| 廠商： | Texas Instruments |
| 文件頁數： | 16/25頁 |
| 文件大小： | 925K |
| 描述： | IC POS HV HOT-SWAP CTRLR 10-MSOP |
| 標準包裝： | 80 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 9 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 配用： | 296-18947-ND - EVAL MODULE FOR TPS2491-002 |
G
GATE
RS
VCC
攖
= I
C
V
?/DIV>
?/DIV>
?/DIV>
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?/DIV>
?/DIV>
?/DIV>
?/DIV>
t +
C
O
V
VCC
I
HAR E
TPS2490
TPS2491
SLVS503D NOVEMBER 2003REVISED JULY 2012
www.ti.com
STEP 6. Choose R5, R6, and C1
R5 is intended to suppress high-frequency oscillations; a resistor of 10& will serve for most applications but if M1
has a C
ISS
below 200 pF, then use 33 &. Applications with larger MOSFETs and short wiring may not require R5.
R6 is required only if the PG output drives a circuit that requires it. It is recommended that the sink current be
less than 2 mA. C1 is a bypass capacitor to help with control of transient voltages, unit emissions, and local
supply noise while in the disabled state. Where acceptable, a value in the range of 0.001 糉 to 0.1 糉 is
recommended.
STEP 7. Choose D1
Transient voltage suppressor D1 is required in applications where there will be enough energy in the distribution
inductance to cause a voltage surge above the TPS2490/91 rated maximum. Such transients can be caused by
card insertions or shorts on the input or output of the TPS2490/91.
ALTERNATIVE INRUSH DESIGNS
Gate Capacitor (dV/dt) Control
The TPS2490/91 can be used with applications that require constant turn-on currents. The current is controlled
by a single capacitor from the GATE terminal to ground with a series resistor. M1 appears to operate as a source
follower (following the gate voltage) in this implementation. Choose a time to charge, 攖, based on the output
capacitor, input voltage V
I
, and desired charge current, I
CHARGE
. Select I
CHARGE
to be less than P
LIM
?V
VCC
if the
power limit feature is kept. See SLVC033 for a calculation tool.
(11)
To select the gate capacitance:
(12)
I
GATE
is the nominal gate charge current. This equation assumes that the MOSFET C
GD
is the controlling element
as the gate and output voltage rise. C
GD
is non-linear with applied V
DG
. An averaged estimate may be made
using the MOSFET V
GS
vs Q
G
curve. Divide the charge accumulated during the plateau region by the plateau
V
GS
to get C
RS
.
Since neither power nor current-limit faults are invoked during turn on, C
T
can be chosen for fast transient turn off
response using the M1 SOA curve. Choose the single pulse time conservatively from the M1 SOA curve using
maximum operating voltage and maximum trip current. A series resistor of about 1 k& should be used in
conjunction with C
G
.
PROG Inrush Control
A capacitor can be connected from the PROG pin to ground to reduce the initial current step seen in Figure 13
based on the Typical Application and Corresponding SOA circuit. This method maintains a relatively fast turn-on
time without the drawbacks of a gate-to-ground capacitor that include increased short circuit response time and
less predictable gate clamping.
ADDITIONAL DESIGN CONSIDERATIONS
Use of PG
Use the PG pin to control and coordinate a downstream dc/dc converter. A long time delay is needed to allow C
O
to fully charge before the converter starts if this is not done. An undesirable latchup condition can be created
between the TPS2490 output characteristic and the dc/dc converter input characteristic if the converter starts
while C
O
is still charging; the PG pin is one way to avoid this.
16
Copyright ?20032012, Texas Instruments Incorporated
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