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參數(shù)資料
| 型號(hào)： | TPS2541RTET |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC16 |
| 封裝： | GREEN, PLASTIC, WQFN-16 |
| 文件頁(yè)數(shù)： | 24/37頁(yè) |
| 文件大小： | 999K |
| 代理商： | TPS2541RTET |
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SLVSAG2A
– OCTOBER 2010 – REVISED APRIL 2011
Layout Guidelines
TPS2540/40A/41 Placement: Place the TPS2540/40A/41 near the USB output connector and 150-
F OUT pin
filter capacitor. Connect the exposed Power PAD to the GND pin and to the system ground plane using a via
array.
IN pin bypass capacitance: Place the 0.1-
F bypass capacitor near the IN pin and make the connection using a
low inductance trace.
D+ and D- Traces: Route in and out traces as controlled impedance differential pairs per the USB specification
and the Intel guideline for USB-2.0. Minimize the use of vias in the high speed data lines.
ESD
The use of a common mode choke in the upstream datapath can provide additional ESD protection from client
side cable insertion transients. In addition, a low capacitance ESD protection array such as the TPD2E001
provides a robust solution. The TPS2540EVM-623 (SLVU401) provides a good example of routing and output
datapath protection.
Using a system board, applying same design rules and protection devices as the TPS2540EVM-623 , the
TPS2540 has been tested to EN61000-4-2. The levels used were 8-kV contact discharge and 15-kV air
discharge. Voltage transients were applied between D+ terminal and the earth ground, and between D- terminal
and the earth ground, V- being connected to earth ground. Tests were performed while both powered and
unpowered. No TPS2540 failures were observed and operation was continuous.
IN Pin Bypass Capacitance
Place the 0.1-
F bypass capacitor near the IN pin and make the connection using a low inductance trace.
ILIM0 and ILIM1 Pin Connections
Current limit set point accuracy can be compromised by stray leakage from a higher voltage source to the ILIM0
or ILIM1 pins. Ensure that there is adequate spacing between IN pin copper/trace and ILIM0 pin trace to prevent
contaminant buildup during the PCB assembly process. If a low current limit set point is required (RILIMx
> 200
k
Ω), use ILIM1 for this case as it is further away from the IN pin.
REVISION HISTORY
Changes from Original (October 2010) to Revision A
Page
Added TPS2540A device to the datasheet. .......................................................................................................................... 1
Deleted All (Draft) notations for BC1.2. ................................................................................................................................ 1
Added Longer Detach Detection Time (TPS2540A) bullet. .................................................................................................. 1
Changed Typical Application Diagram. ................................................................................................................................. 1
Added TPS2540A description information. ........................................................................................................................... 2
Added Low DP_IN period in DCP mode information for the TPS2540A device .................................................................. 6
Changed pinout drawing. ...................................................................................................................................................... 7
Changed TPS2540/40A Control Signal drawing. ................................................................................................................ 29
30
Copyright
2010–2011, Texas Instruments Incorporated
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