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參數資料
| 型號： | TPS3106K12DVB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ULTRALOW SUPPLY CURRENT/SUPPLY VOLTAGE SUPERVISORY CIRCUITS |
| 中文描述： | 超低電源電流/電源電壓監(jiān)控電路 |
| 文件頁數： | 12/22頁 |
| 文件大小： | 361K |
| 代理商： | TPS3106K12DVB |
SLVS363B AUGUST 2001 REVISED SEPTEMBER 2004
www.ti.com
12
TIMING REQUIREMENTS AT R
L
= 1 M
, C
L
= 50 PF, T
A
= 40
°
C TO 85
°
C
PARAMETER
VDD
≥
0.85 V
at VDD
VIH = 1.1
×
VIT, VIL = 0.9
×
VIT, VIT = 0.86 V
at MR
VDD
≥
VIT + 0.2 V, VIL = 0.3
×
VDD,
at SENSE
VDD
≥
VIT,
tw
Pulse width
at PFI
VDD
≥
0.85 V,
at WDI
VDD
≥
VIT,
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tt(out)
Time-out period
at WDI
0.55
1.1
1.65
s
20
VIH = 0.7
×
VDD
0.1
VIH = 1.1
×
VIT(S), VIL = 0.9
×
VIT(S)
VIH = 1.1
×
VIT(S),VIL = 0.9
×
VIT(S)
VIL = 0.3
×
VDD,
20
μ
s
20
VIH = 0.7
×
VDD
0.3
SWITCHING CHARACTERISTICS AT R
L
= 1 M
, C
L
= 50 PF, T
A
= 40
°
C TO 85
°
C
PARAMETER
TEST CONDITIONS
VDD
≥
1.1
×
VIT,
MR = 0.7
×
VDD,
See timing diagram
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VDD
≥
0.8 V,
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VDD
≥
0.8 V,
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VDD
≥
0.8 V,
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VDD
≥
0.8 V,
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
MIN
TYP
MAX
UNIT
td
Delay time
65
130
195
ms
tPHL
Propagation delay time, high-to-low level output
VDD to RESET or
RSTVDD delay
VDD to RESET or
RSTVDD delay
40
μ
s
tPLH
Propagation delay time, low-to-high level output
40
tPHL
Propagation delay time, high-to-low level output
SENSE to RESET or
RSTSENSE delay
40
μ
s
tPLH
Propagation delay time, high-to-low level output
SENSE to RESET or
RSTSENSE delay
40
μ
s
tPHL
Propagation delay time, high-to-low level output
PFI to PFO delay
40
μ
s
tPLH
Propagation delay time, low-to-high level output
PFI to PFO delay
300
μ
s
tPHL
Propagation delay time, low-to-high level output
MR to RESET.
RSTVDD,
RSTSENSE delay
VDD
≥
1.1
×
VIT
VIL = 0.3
×
VDD,
VIH = 0.7
×
VDD
1
5
tPLH
Propagation delay time, low-to-high level output
MR to RESET.
RSTVDD,
RSTSENSE delay
μ
s
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