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參數資料
| 型號： | TPS3514DG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 3-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14 |
| 封裝： | GREEN, PLASTIC, SOIC-14 |
| 文件頁數： | 17/17頁 |
| 文件大?。?/td> | 585K |
| 代理商： | TPS3514DG4 |
www.ti.com
DETAILED DESCRIPTION
Power-Good and Power-Good Delay
t2
t3
t5
t4
5V/3.3V
Output
PSON
PGO
On
Off
75%
10%
SLVS422C – JUNE 2002 – REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
T
A = +25°C, unless otherwise noted.
NORMALIZED SENSE THRESHOLD VOLTAGE
CURRENT RATIO
vs
FREE-AIR TEMPERATURE AT VDD
FREE-AIR TEMPERATURE
Although there is no requirement to meet specific
timing parameters, the following signal timings are
recommended:
A PC power supply is commonly designed to provide
a power-good signal, which is defined by the
2ms
≤ t
2 ≤ 20ms, 100ms < t3 < 2000ms, t4 >
computer manufacturers. Power-Good Output (PGO)
1ms, t5 ≤ 10ms
is a power-good indicator and should be asserted
Furthermore, motherboards should be designed to
high by the PC power supply to indicate that the
comply with the above recommended timing. If
5VDC
and
3.3VDC
outputs
are
above
the
timings
other
than
these
are
implemented
or
under-voltage threshold limit. At this time, the supply
required, this information should be clearly specified.
should be able to provide enough power to assure
continuous operation within the specification.
The TPS3514 family of power-supply supervisors
provides a PGO for the 3.3V and 5V supply voltage
Conversely, when either the 5VDC or the 3.3VDC
rails and a separate Power-Good Input (PGI). An
output
voltages
fall
below
the
under-voltage
internal
timer
is
used
to
generate
a
300ms
threshold, or when main power has been removed
power-good delay.
for a sufficiently long time so that power-supply
operation is no longer assured, PGO should be
deasserted to a low state. The power-good, DC
enable (PSON), and the 5V/3.3V supply rails are
shown in Figure 3.
Figure 3. Timing of PSON and PGO
9
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