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參數資料
| 型號： | TPS3808G33MDBVREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6 |
| 封裝： | GREEN, PLASTIC, SOT-23, 6 PIN |
| 文件頁數： | 14/15頁 |
| 文件大小： | 530K |
| 代理商： | TPS3808G33MDBVREP |
DEVICE OPERATION
SENSE INPUT
RESET OUTPUT
V
IN
TPS3808G01
V
DD
SENSE
GND
RESET
R
1
R
2
1nF
V
=(1+)0.405
IT
R1
R2
V
OUT
MANUAL RESET (MR) INPUT
2.5V
T PS 380 8G 25
O M AP 1510
V
DD
SENSE
V
DDSHV 1, 3, 6, 7, 9
GND
C
T
MR
RESET
1M
RESPWRON
SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................. www.ti.com
supply line can be used to allow the reset signal for
The TPS3808 microprocessor supervisory product
the microprocessor to have a voltage higher than VDD
family is designed to assert a RESET signal when
(up to 6.5 V). The pullup resistor should be no
either the SENSE pin voltage drops below VIT or the
smaller than 10 k
as a result of the finite impedance
manual reset (MR) is driven low. The RESET output
of the RESET line.
remains asserted for a user-adjustable time after both
the manual reset (MR) and SENSE voltages return
above the respective thresholds. A broad range of
voltage threshold and reset delay time adjustments
The SENSE input provides a terminal at which any
are available, allowing these devices to be used in a
system voltage can be monitored. If the voltage on
wide array of applications. Reset threshold voltages
this pin drops below VIT, then RESET is asserted.
can be factory-set from 0.82 V to 3.3 V or from 4.4 V
The comparator has a built-in hysteresis to ensure
to 5.0 V, while the TPS3808G01 can be set to any
smooth RESET assertions and de-assertions. It is
voltage above 0.405 V using an external resistor
good analog design practice to put a 1-nF to 10-nF
divider.
Two
preset
delay
times
are
also
bypass capacitor on the SENSE input to reduce
user-selectable: connecting the CT pin to VDD results
sensitivity to transients and layout parasitics.
in a 300ms reset delay, while leaving the CT pin open
The TPS3808G01 can be used to monitor any
yields a 20-ms reset delay. In addition, connecting a
voltage rail down to 0.405 V using the circuit shown
capacitor between CT and GND allows the designer
in Figure 11.
to select any reset delay period from 1.25 ms to 10 s.
A typical application of the TPS3808G25 used with
the OMAP1510 processor is shown in Figure 10. The
open-drain RESET output is typically connected to
the RESET input of a microprocessor. A pullup
resistor must be used to hold this line high when
RESET is not asserted. The RESET output is
undefined for voltage below 0.8 V, but this is normally
not a problem since most microprocessors do not
function below this voltage. RESET remains high
(unasserted) as long as SENSE is above its threshold
Figure 11. Using the TPS3808G01 to Monitor a
(VIT) and the manual reset (MR) is logic high. If either
User-Defined Threshold Voltage
SENSE falls below VIT or MR is driven low, RESET is
asserted, driving the RESET pin to a low impedance.
The manual reset (MR) input allows a processor or
other logic circuits to initiate a reset. A logic low
(0.3 VDD) on MR causes RESET to assert. After MR
returns to a logic high and SENSE is above its reset
threshold, RESET is de-asserted after the user
defined reset delay expires. Note that MR is internally
tied to VDD using a 90-k resistor so this pin can be
left unconnected if MR will not be used.
See Figure 12 for how MR can be used to monitor
multiple system voltages. Note that if the logic signal
driving MR does not go fully to VDD, there will be
Figure 10. Typical Application of the TPS3808
with an OMAP Processor
some additional current draw into VDD as a result of
the internal pullup resistor on MR. To minimize
current draw, a logic-level FET can be used as
Once MR is again logic high and SENSE is above VIT
illustrated in Figure 13.
+ VHYS (the threshold hysteresis), a delay circuit is
enabled which holds RESET low for a specified reset
delay period. Once the reset delay has expired, the
RESET pin goes to a high impedance state. The
pullup resistor from the open-drain RESET to the
8
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS3808-EP
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相關代理商/技術參數 |
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| TPS3808G33QDBVRMO | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| TPS3808G33QDBVRQ1 | 功能描述:監控電路 Lo Quies Current Pro Delay Sup Circuit RoHS:否 制造商:STMicroelectronics 監測電壓數: 監測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TPS3808G50DBVR | 功能描述:監控電路 Programmable-Delay Supervisory RoHS:否 制造商:STMicroelectronics 監測電壓數: 監測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TPS3808G50DBVRG4 | 功能描述:監控電路 Programmable-Delay Supervisory RoHS:否 制造商:STMicroelectronics 監測電壓數: 監測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TPS3808G50DBVT | 功能描述:監控電路 Programmable-Delay Supervisory RoHS:否 制造商:STMicroelectronics 監測電壓數: 監測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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