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參數資料
| 型號： | TPS3837H30 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TRANS NPN BIPOLAR 65V SOT-323 |
| 中文描述： | NANOPOWER監控電路 |
| 文件頁數： | 7/11頁 |
| 文件大小： | 173K |
| 代理商： | TPS3837H30 |
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A
–
JUNE 2000
–
REVISED JANUARY 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements at R
L
= 1 M
, C
L
= 50 pF, T
A
= 25 C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
at VDD
VIH = VIT + 0.2 V,
VDD
≥
VIT + 0.2 V,
VIH = 0.7
×
VDD
VIL = VIT
–
0.2 V
VIL = 0.3
×
VDD,
6
μ
s
tw
Pulse width
at MR
1
μ
s
switching characteristics at R
L
= 1 M
, C
L
= 50 pF, T
A
= 25 C
PARAMETER
TEST CONDITIONS
VDD
≥
VIT + 0.2 V,
MR = 0.7
×
VDD,
CT = GND,
See timing diagram
VDD
≥
VIT + 0.2 V,
MR = 0.7
×
VDD,
CT = VDD ,
See timing diagram
VIL = VIT
–
0.2 V,
VIH = VIT + 0.2 V
VIL = 1.6 V
VIL = VIT
–
0.2 V,
VIH = VIT + 0.2 V
VIL = 1.6 V
VDD
≥
VIT + 0.2 V,
VIL = 0.3
×
VDD,
VIL = 0.7
×
VDD
MIN
TYP
MAX
UNIT
td
Delay time
5
10
15
ms
100
200
300
tPHL
Propagation (delay) time, high-to-low-level output
Pro agation (delay) time, high to low level out ut
VDD to RESET delay
(TPS3836 TPS3838)
(TPS3836, TPS3838)
10
μ
s
50
tPLH
Propagation (delay) time, low-to-high-level output
Pro agation (delay) time, low to high level out ut
VDD to RESET delay
(TPS3837)
10
μ
s
50
tPHL
Propagation (delay) time, high-to-low-level output
MR to RESET delay
(TPS3836, TPS3838)
0.1
μ
s
tPLH
Propagation (delay) time, low-to-high-level output
MR to RESET delay
(TPS3837)
0.1
μ
s
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IDD
IMR
VOL
VOH
Supply current
vs Supply voltage
1
Manual reset current
vs Manual reset voltage
2
Low-level output voltage
vs Low-level output current
3
High-level output voltage
vs High-level output current
4
Normalized reset threshold voltage
vs Free-air temperature
5
Minimum pulse duration at VDD
vs VDD Threshold overdrive
6
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