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參數資料
| 型號： | TPS40070PWPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | GREEN, PLASTIC, HTSSOP-16 |
| 文件頁數： | 24/28頁 |
| 文件大小： | 655K |
| 代理商： | TPS40070PWPR |
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THERMAL
PAD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
KFF
RT
LVBP
PGD
SGND
SS
FB
COMP
ILIM
VDD
BOOST
HDRV
SW
DBP
LDRV
PGND
PWP PACKAGE(1)(2)
(TOP VIEW)
www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
(1)
For more information on the PWP package, refer to TI Technical Brief (SLMA002).
(2)
PowerPAD heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.
Table 1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Gate drive voltage for the high-side N-channel MOSFET. The BOOST voltage is 8 V greater than the input
BOOST
14
I
voltage. A capacitor should be connected from this pin to the SW pin.
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
COMP
8
O
FB pin to compensate the overall loop. The comp pin is internally clamped to 3.4 V.
8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be bypassed to
DBP
11
O
ground with a 1.0-
F ceramic capacitor.
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference
FB
7
I
voltage, 0.7 V.
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
HDRV
13
O
(MOSFET off).
Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sink
from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltage
on this pin is compared to the voltage drop (VVDD -VSW) across the high side N-channel MOSFET during
ILIM
16
I
conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately VDD/2 and released
when SW is within 2 V of VDD or after a timeout (the precondition time) - whichever occurs first. Placing a
capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time,
effectively programming the ILIM blanking time. See applications information.
A resistor is connected from this pin to VIN programs the amount of feed-forward voltage. The current fed into this
KFF
1
I
pin is internally divided by 25 and used to control the slope of the PWM ramp and program undervoltage lockout.
Nominal voltage at this pin is maintained at 400 mV.
Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground (MOSFET
LDRV
10
O
off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC.
4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1-
F ceramic capacitor.
LVBP
3
O
External loads less than 1 mA and electrically quiet may be applied.
This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a 10%
PGD
4
O
band around VREF.
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the
PGND
9
lower MOSFET(s).
RT
2
I
A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
SGND
5
Signal ground reference for the device.
Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The
capacitor is charged with an internal current source of 10
A. The resulting voltage ramp on the SS pin is used as
a second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V
SS
6
I
less that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the
SS pin reaches the internal reference voltage of 1 V plus the internal reference voltage of 0.7 V. If SS is below the
1-V offset voltage to the error amplifier. The resulting output voltage is zero. Also provides timing for fault recovery
attempts. Maximum recommended capacitor value is 22nF.
This pin is connected to the switched node of the converter. It is used for short circuit sensing, gate drive timing
SW
12
I
information and is the return for the high side driver. A 1.5-
resistor is required in series with this pin for
protection against substrate current issues.
VDD
15
I
Supply voltage for the device.
Copyright 2003–2009, Texas Instruments Incorporated
5
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