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參數資料
| 型號： | TPS40077PWPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | GREEN, PLASTIC, HTSSOP-16 |
| 文件頁數： | 9/43頁 |
| 文件大小： | 847K |
| 代理商： | TPS40077PWPG4 |
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PROGRAMMING SHORT-CIRCUIT PROTECTION
ILIM Threshold
T2
T1
ILIM Threshold
T3
T1
ILIM
SW
VIN 2V
UDG03173
Overcurrent
(A)
(B)
www.ti.com ..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
The TPS40077 uses a two-tier approach for short-circuit protection. The first tier is a pulse-by-pulse protection
scheme. Short-circuit protection is implemented on the high-side MOSFET by sensing the voltage drop across
the MOSFET when its gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor (RILIM) connected from VVDD to the ILIM pin when driven by a constant-current sink. If the voltage drop
across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately
terminated. The MOSFET remains off until the next switching cycle is initiated. This is illustrated in Figure 24.
Figure 24. Switching and Current-Limit Waveforms and Timing Relationship
In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half of
VVDD. The ILIM pin is allowed to return to its nominal value after one of two events occurs. If the SW node rises
to within approximately 2 V of VVDD, the device allows ILIM to go back to its nominal value. This is illustrated in
Figure 24(A). T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includes
a driver delay of 50 ns, typical. T2 is the reaction time of the sensing circuit that allows ILIM to start to return to
its nominal value, typically 20 ns. The second event that can cause ILIM to return to its nominal value is for an
internal timeout to expire. This is illustrated in Figure 24(B) as T3. Here SW never rises to VVDD – 2 V, for
whatever reason, and the internal timer times out, releasing the ILIM pin.
Prior to ILIM starting back to its nominal value, overcurrent sensing is not enabled. In normal operation, this
ensures that the SW node is at a higher voltage than ILIM when overcurrent sensing starts, avoiding false trips
while allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across RILIM
sets an exponential approach to the normal voltage at the ILIM pin. This exponential decay of the overcurrent
threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate
for slower-turnon FETs. Choosing the proper capacitance requires care. If the capacitance is too large, the
voltage at ILIM does not approach the desired overcurrent level quickly enough, resulting in an apparent shift in
overcurrent threshold as pulse duration changes. As a general rule, it is best to make the time constant of the
R-C at the ILIM pin 0.2 times or less of the nominal pulse duration of the converter as shown in Equation 11.
Also, the comparator that uses ILIM and SW to determine if an overcurrent condition exists has a clamp on its
SW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as
much as 2 V at –40°C) below VVDD. When ILIM is more than 1.4 V below VVDD, the overcurrent circuit is
effectively disabled.
Copyright 2007–2009, Texas Instruments Incorporated
17
Product Folder Link(s) :TPS40077
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