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參數資料
| 型號： | TPS5102IDBR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數： | 21/31頁 |
| 文件大小： | 1083K |
| 代理商： | TPS5102IDBR |
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
synchronization (continued)
Ct
Rt
TPS5102
An external resistor is added into the circuit, but Rt is still removed. Ct is kept to be a part of RC circuit generating
triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the
capacitor can be adjusted to achieve the correct peak-to-peak value and the offset value.
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output,
then back to the driver section and, finally, parallel the low-level components. Below are several specific points
to consider beforethe layout of a TPS5102 design begins.
All sensitive analog components should be referenced to ANAGND. These include components connected
to Vref5, Vref, INV, LH, and COMP.
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on V
O
, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
The bypass capacitor for V
CC
should be placed close to the TPS5102.
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS5102.
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.
The bulk storage capacitors across V
In
should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
High-frequency bypass capacitors should be placed across the bulk storage capacitors on V
O
.
LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces.
The output voltage sensing trace should be isolated by either ground trace or Vcc trace.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TPS5102IDBT | 功能描述:DC/DC 開關控制器 Dual Output Synch Buck Controller RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| TPS5102IDBTG4 | 功能描述:DC/DC 開關控制器 Dual Output Synch Buck Cntrlr RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| TPS5102IDBTR | 功能描述:DC/DC 開關控制器 Dual Output Synch Buck Cntrlr RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| TPS5102IDBTRG4 | 功能描述:DC/DC 開關控制器 Dual Output Synch Buck Cntrlr RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| TPS5103 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER |
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