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參數資料
| 型號： | TPS51200DRCT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO10 |
| 封裝： | GREEN, PLASTIC, VSON-10 |
| 文件頁數： | 9/35頁 |
| 文件大小： | 1131K |
| 代理商： | TPS51200DRCT |
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LAYOUT CONSIDERATIONS
SLUS812 – FEBRUARY 2008
For further information regarding the PowerPAD package and the recommended board layout, refer to the
PowerPAD package application note (SLMA002). This document is available at www.ti.com.
Consider the following points before starting the TPS51200 layout design.
The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide
connections.
The output capacitor for VO should be placed close to the pin with short and wide connection in order to
avoid additional ESR and/or ESL trace inductance.
VOSNS should be connected to the positive node of VO output capacitor(s) as a separate trace from the high
current power line. This configuration is strongly recommended to avoid additional ESR and/or ESL. If
sensing the voltage at the point of the load is required, it is recommended to attach the output capacitor(s) at
that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between the
GND pin and the output capacitor(s).
Consider adding low-pass filter at VOSNS if the ESR of the VO output capacitor(s) is larger than 2 m.
REFIN can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of REFOUT. Avoid any noise-generating lines.
The negative node of the VO output capacitor(s) and the REFOUT capacitor should be tied together by
avoiding common impedance to the high current path of the VO source/sink current.
The GND and PGND pins should be connected to the thermal land underneath the die pad with multiple vias
connecting to the internal system ground planes (for better result, use at least two internal ground planes).
Use as many vias as possible to reduce the impedance between PGND/GND and the system ground plane.
Also, place bulk caps close to the DIMM load point, route the VOSNS to the DIMM load sense point.
In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly
to the package’s thermal pad. The wide traces of the component and the side copper connected to the
thermal land pad help to dissipate heat. Numerous vias 0,33 mm in diameter connected from the thermal land
to the internal/solder side ground plane(s) should also be used to help dissipation.
Please consult the TPS51200-EVM User's Guide (SLUUxxx) for detailed layout recommendations.
Copyright 2008, Texas Instruments Incorporated
17
Product Folder Link(s): TPS51200
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TPS51200DRCT | 制造商:Texas Instruments 功能描述:IC DDR TERMINATION REGULATOR 3A SON10 制造商:Texas Instruments 功能描述:IC, DDR TERMINATION REGULATOR, 3A, SON10 |
| TPS51200DRCTG4 | 功能描述:低壓差穩壓器 - LDO Sink/Source DDR Term Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節:0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TPS51200EVM | 功能描述:電源管理IC開發工具 TPS51200 Sink Source DDR Term Reg RoHS:否 制造商:Maxim Integrated 產品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| TPS51200MDRCTEP | 功能描述:- Converter, DDR Voltage Regulator IC 1 Output 10-VSON (3x3) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態:新產品 應用:轉換器，DDR 電壓 - 輸入:2.38 V ~ 3.5 V 輸出數:1 電壓 - 輸出:- 工作溫度:-55°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:10-VFDFN 裸露焊盤 供應商器件封裝:10-VSON（3x3） 標準包裝:1 |
| TPS51200-Q1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SINK/SOURCE DDR TERMINATION REGULATOR |
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