
SW
0
OUT
f
1
f
2
ESR
C
4
=
p
(4)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
f
OUT
IN max
IND ripple
IN max
OUT max
IN max
V
1
3
L
I
V
I
V
-
-
=
=
(5)
OUT
RIPPLE
1.5%
ESR
V
I
=
(6)
SLUS843B – MAY 2008 – REVISED SEPTEMBER 2008 .................................................................................................................................................. www.ti.com
For loop stability, the 0-dB frequency, f0, defined in Equation 4 must be lower than of the switching frequency. As f0 is determined solely by the output capacitor’s characteristics, loop stability of D-CAP mode is determined by
the capacitor’s chemistry. For example, the output capacitance of specialty polymer capacitors (SP-CAP) is on
the order of several hundred microfarads and an ESR of approximately 10 m
. These values yield a 0-dB
frequency of 100 kHz or less and the loop is stable. However, ceramic capacitors yield a f0 at more than 700 kHz
which is not suitable for this operational mode.
Although D-CAP mode provides many advantages such as ease-of-use, minimum external components, and
extremely fast transient response, a sufficient amount of feedback signal needs to be provided to reduce the jitter
level. In a TPS51427A design, it is generally recommended to optimize the output voltage ripple at around 1.5%
of the targeted DC voltage in both Auto-skip and PWM mode operations. For example, if VVOUT1 = 1.5 V, the
desired output ripple should be at least 1.5 V x 1.5% = 22.5 mV. This can be achieved by taking advantage of
the output bulk capacitor ESR.
The external component selection is much simpler in D-CAP mode. Below is a simplified design procedure
targeting to the customers that are very familiar with SMPS design.
1. Determine the output voltage setting.
For the fixed 5 V/3.3 V option, tie VFB1 pin to GND and REFIN2 to V5FILT. For the fixed 1.5 V/1.05 V
configuration, tie VFB1 to V5FILT and REFIN2 to VREF3. TPS51427A also supports adjustable voltage
options for both channels. The adjustable range for Channel1 is between 0.7 V and 5.9 V and for Channel2
is between 0.5 V and 2.5 V.
Figure 46 shows how to configure the adjustable voltage option for Channel1
and
Figure 47 shows the configuration for Channel2. Also, equations are provided in
Table 5 to aid the
design process.
2. Choose the output inductor.
Output inductance is a function of VIN, VOUT, fSW and the desired ripple current. For available switching
frequency settings with TPS51427A, refer to
Table 2. The process of choosing the right output inductance is
an iterative one; many considerations need to be taken, such as the desired transient response, efficiency
over the entire load range, load/line regulation, component availability and cost. Base the initial output
inductance value upon where the ripple current is 25% to 50% of the maximum loading current. For transient
optimized design, ripple factor can be higher; and for efficiency and load/line regulation optimized design, the
ripple factor can be lower.
3. Choose the output capacitor(s).
Organic semiconductor capacitors or specialty polymer capacitor(s) are recommended. Determine ESR to
meet the required ripple voltage indicated previous.
32
Copyright 2008, Texas Instruments Incorporated