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參數資料
| 型號： | TPS5210DWR |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Voltage-Mode SMPS Controller |
| 中文描述： | 電壓模式開關電源控制器 |
| 文件頁數： | 3/29頁 |
| 文件大?。?/td> | 500K |
| 代理商： | TPS5210DWR |
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TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
ANAGND
NO.
7
Analog ground
Analog BIAS pin. A 1-
μ
F ceramic capacitor should be connected from BIAS to ANAGND.
Bootstrap. Connect a 1-
μ
F low-ESR capacitor from BOOT to BOOTLO.
Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive
configuration. Connect BOOTLO to PGND for ground reference drive configuration.
BIAS
9
O
BOOT
16
I
BOOTLO
18
O
DROOP
2
I
Droop voltage. Voltage input used to set the amount of output-voltage set-point droop as a function of load
current. The amount of droop compensation is set with a resistor divider between IOUT and ANAGND.
DRV
14
O
Drive regulator for the FET drivers. A 1-
μ
F ceramic capacitor should be connected from DRV to DRVGND.
Drive ground. Ground for FET drivers. Connect to FET PWRGND.
DRVGND
12
HIGHDR
17
O
High drive. Output drive to high-side power switching FETs
HISENSE
19
I
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for
optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with
high-side FET drain.
INHIBIT
22
I
Disables the drive signals to the MOSFET drivers. Can also serve as UVLO for system logic supply (either 3.3 V
or 5 V).
IOUT
1
O
Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the
high-side FETs. The voltage on this pin equals 2
×
R
ds(on)
×
IOUT. In applications where very accurate current
sensing is required, a sense resistor should be connected between the input supply and the drain of the high-side
FETs.
IOUTLO
21
O
Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic
capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FETs
are off. Capacitance range should be between 0.033
μ
F and 0.1
μ
F.
Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low.
LODRV
10
I
LOHIB
11
I
Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and
eliminate shoot-through current. Disabled when configured in crowbar mode.
LOSENSE
20
I
Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for
optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series
with high-side FET drain.
LOWDR
13
O
Low drive. Output drive to synchronous rectifier FETs
OCP
3
I
Over current protection. Current limit trip point is set with a resistor divider between IOUT and
ANAGND.
PWRGD
28
O
Power good. Power Good signal goes high when output voltage is within 7% of voltage set by VID pins.
Open-drain output.
SLOWST
8
O
Slow Start (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.
Slowstart current = I
VREFB
/5
12-V supply. A 1-
μ
F ceramic capacitor should be connected from VCC to DRVGND.
HYSTERESIS set pin. The hysteresis is set with a resistor divider from VREFB to ANAGND.
The hysteresis window = 2
×
(VREFB – VHYST)
Voltage Identification input 0
V
CC
VHYST
15
4
I
VID0
27
I
VID1
26
I
Voltage Identification input 1
VID2
25
I
Voltage Identification input 2
VID3
24
I
Voltage Identification input 3
VID4
23
I
Voltage Identification input 4. Digital inputs that set the output voltage of the converter. The code pattern for
setting the output voltage is located in Table 1. Internally pulled up to 5 V with a resistor divider biased from VCC
.
Buffered reference voltage from VID network
VREFB
5
O
VSENSE
6
I
Voltage sense Input. To be connected to converter output voltage bus to sense and control output voltage. It is
recommended an RC low pass filter be connected at this pin to filter noise.
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