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參數資料
| 型號： | TPS53127RGER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, 700 kHz SWITCHING FREQ-MAX, PQCC24 |
| 封裝： | GREEN, PLASTIC, VQFN-24 |
| 文件頁數： | 26/29頁 |
| 文件大小： | 861K |
| 代理商： | TPS53127RGER |
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VBST1
EN1
VO1
VFB1
GND
SS1
VFB2
VO2
EN2
VBST2
DRVH1
SW1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
SS2
TRIP2
PGND2
DRVL2
SW2
DRVH2
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
16
15
14
13
TSSOP PACKAGE
(TOP VIEW)
TRIP1
VIN
VO1
VFB1
GND
SS1
VREG5
V5 FILT
SS 2
TRIP2
VFB2
VO2
E
N
2
E
N
1
V
B
S
T
1
D
R
V
H
1
S
W
1
D
R
V
L
1
P
G
N
D
1
V
B
S
T
2
D
R
V
H
2
S
W
2
D
R
V
L
2
P
G
N
D
2
16
15
14
13
18
17
1
2
3
4
5
6
9
1
0
1
2
7
8
2
3
2
0
2
4
2
1
9
QFN PACKAGE
(TOP VIEW)
SLVSA93 – MARCH 2010
www.ti.com
PIN Fucntion Table (continued)
TERMINAL
I/O
DESCRIPTION
QFN
TSSOP
NAME
24
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single
GND
3
6
I
point.
DRVH1,
High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers
22, 9
1, 12
O
DRVH2
switch between SWx (OFF) and VBSTx (ON).
Switch node connections for both the high-side drivers and the over current
SW1, SW2
21, 10
24, 13
I/O
comparators.
DRVL1,
Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers
20, 11
23, 14
O
DRVL2
switch between PGNDx (OFF) and VREG5 (ON).
Power ground connections for both the low-side drivers and the over current
PGND1,
19, 12
22, 15
I/O
comparators. Connect PGND1, PGND2 and GND strongly together near the
PGND2
IC.
TRIP1,
Over current threshold programming pin. Connect to GND with a resistor to
18, 13
21, 16
I
TRIP2
GND to set threshold for low-side RDS(ON) current limit.
Supply Input for 5-V linear regulator. Bypass to GND with a minimum
VIN
17
20
I
high-quality 0.1-mF ceramic capacitor.
5-V supply input for the entire control circuitry except the MOSFET drivers.
V5FILT
15
18
I
Bypass to GND with a minimum high-quality 1.0-mF ceramic capacitor. V5FILT
is connected to VREG5 via an internal 10-
resistor.
Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND
VREG5
16
19
O
with a minimum high-quality 4.7-mF ceramic capacitor. VREG5 is connected to
V5FILT via an internal 10-
resistor.
Soft-start programming pin. Connect capacitor from SSx pin to GND to program
SS1, SS2
4,14
7, 17
O
soft-start time.
6
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53127
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