
SLUSA68 – DECEMBER 2010
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When the load is increased, the inductor current is always positive and the zero-crossing comparator does not
send a zero-crossing signal. The converter enters into continuous conduction mode (CCM) when no
zero-crossing is detected for two consecutive PWM pulses. The switching synchronizes to the internal clock and
the switching frequency is fixed.
In high-efficiency mode (HEF), the operation is the same as diode emulation mode at light load. However, the
converter does not synchronize to the internal clock during CCM. Instead, the PWM modulator determines the
switching frequency.
Eco-mode Light-Load Operation
In skip modes (DE and HEF) when the load current is less than one-half of the inductor peak current, the
inductor current becomes negative by the end of off-time. During light load operation, the low-side MOSFET is
turned off when the inductor current reaches zero. The energy delivered to the load per switching cycle is
increased compared to the normal PWM mode operation and the switching frequency is reduced. The switching
loss is reduced, thereby improving efficiency.
In both DE and HEF mode, the switching frequency is reduced in discontinuous conduction mode (DCM). When
the load current is 0 A, the minimum switching frequency is reached. The difference between VVBST and VSW
must be maintained at a value higher than 2.4 V.
Forced Continuous Conduction Mode (FCCM)
When the PS pin is grounded or greater than 2.2 V, the TPS53310 is operating in forced continuous conduction
mode in both light-load and heavy-load conditions. In this mode, the switching frequency remains constant over
the entire load range, making it suitable for applications that need tight control of switching frequency at a cost of
lower efficiency at light load.
Soft Start
The soft-start function reduces the inrush current during the start up sequence. A slow-rising reference voltage is
generated by the soft-start circuitry and sent to the input of the error amplifier. When the soft-start ramp voltage
is less than 600 mV, the error amplifier uses this ramp voltage as the reference. When the ramp voltage reaches
600 mV, the error amplifier switches to a fixed 600-mV reference. The typical soft-start time is 400 s.
Power Good
The TPS53310 monitors the voltage on the FB pin. If the FB voltage is between 83% and 117% of the reference
voltage, the power good signal remains high. If the FB voltage falls outside of these limits, the internal open drain
output pulls the power good pin (PGD) low.
During start-up, VIN needs to be higher than 1-V in order to have valid power good logic, and the power good
signal is delayed for 400 s after the FB voltage falls to within the power good limits. There is also 10-s delay
during the shut down sequence.
Undervoltage Lockout (UVLO) Function
The TPS53310 provides undervoltage lockout (UVLO) protection for both power input (VIN) and bias input (VDD)
voltage. If either of them is lower than the UVLO threshold voltage minus the hysteresis, the device shuts off.
When the voltage rises above the threshold voltage, the device restarts. The typical UVLO rising threshold is 2.8
V for both VIN and VVDD. A hysteresis voltage of 130 mV for VIN and 75 mV for VVDD is also provided to prevent
glitch.
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