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參數(shù)資料
| 型號： | TPS54073PWPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 25 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大小： | 850K |
| 代理商： | TPS54073PWPRG4 |
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GROUNDING AND PowerPAD LAYOUT
UNDERVOLTAGE LOCKOUT (UVLO)
SLOW-START/ENABLE (SS/ENA)
t
d +
C
(SS)
1.2 V
5 mA
(27)
t
(SS) +
C
(SS)
0.7 V
5 mA
(28)
VBIAS REGULATOR (VBIAS)
SLVS547 – FEBRUARY 2005 ............................................................................................................................................................................................ www.ti.com
The TPS54073 has two internal grounds (analog and power). Inside the TPS54073, the analog ground ties to all
of the noise-sensitive signals, whereas the power ground ties to the noisier power signals. The PowerPAD must
be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the
TPS54073, particularly at higher output currents. However, ground noise on an analog ground plane can also
cause problems with some of the control and bias signals. For these reasons, separate analog and power ground
planes are recommended. These two planes must tie together directly at the IC to reduce noise between the two
grounds. The only components that must tie directly to the power ground plane are the input capacitor, the output
capacitor, the input voltage de-coupling capacitor, and the PGND pins of the TPS54073.
The TPS54073 incorporates an undervoltage-lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator,
and a 2.5-
s rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise
on VIN. UVLO is with respect to VIN and not PVIN, see the Application Information section.
The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-
s falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and AGND.
Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the
SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The start-up delay is approximately:
Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
The actual slow-start time is likely to be less than the above approximation due to the brief ramp-up at the
internal rate.
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high-quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V,
and external loads on VBIAS with ac or digital-switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits. VBIAS is derived from the VIN pin; see the functional block
diagram of this data sheet.
18
Copyright 2005, Texas Instruments Incorporated
Product Folder Link(s): TPS54073
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| TPS5410 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1-A, WIDE INPUT RANGE, STEP-DOWN SWIFT CONVERTER |
| TPS5410D | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 5.5V to 36V Input 1A Step Down Conv RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS5410DG4 | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 5.5V to 36V Input 1A Step Down Conv RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS5410DR | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 5.5V-36V Input 1A Step Down Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS5410DRG4 | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 5.5V-36V Input 1A Step Down Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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