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參數資料
型號: TPS54140QDRCRQ1
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩壓器
英文描述: SWITCHING REGULATOR, PDSO10
封裝: GREEN, PLASTIC, SON-10
文件頁數: 3/50頁
文件大小: 1602K
代理商: TPS54140QDRCRQ1
SLVSA24B
– OCTOBER 2009 – REVISED MARCH 2011
OVERVIEW
The TPS54140 device is a 42-V, 1.5-A, step-down (buck) regulator with an integrated high side n-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100kHz to 2500kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The TPS54140 has a default start up voltage of approximately 2.5V. The EN pin has an internal pull-up current
source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external
resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device will
operate. The operating current is 116
μA when not switching and under no load. When the device is disabled, the
supply current is 1.3
μA.
The integrated 200m
high side MOSFET allows for high efficiency power supply designs capable of delivering
1.5 amperes of continuous current to a load. The TPS54140 reduces the external component count by
integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the
high side MOSFET off when the boot voltage falls below a preset threshold. The TPS54140 can operate at high
duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V
reference.
The TPS54140 has a power good comparator (PWRGD) which asserts when the regulated output voltage is less
than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which
deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the
pin to transition high when a pull-up resistor is used.
The TPS54140 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power
good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from
turning on until the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,
UVLO fault or a disabled condition.
The TPS54140, also, discharges the slow start capacitor during overload conditions with an overload recovery
circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation
voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during
startup and overcurrent fault conditions to help control the inductor current.
Copyright
2009–2011, Texas Instruments Incorporated
11
Product Folder Link(s): TPS54140-Q1
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