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參數資料
| 型號： | TPS54225TPWPRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | SWITCHING REGULATOR, PDSO14 |
| 封裝： | PLASTIC, TSSOP-14 |
| 文件頁數： | 16/18頁 |
| 文件大小： | 354K |
| 代理商： | TPS54225TPWPRQ1 |
Tss(ms)=
C6(nF) Vref
Iss( A)
=
C6(nF) 0.765
2
SLVSAV9
– JUNE 2011
shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP2
mode control.
PWM Frequency and Adaptive On-Time Control
TPS54225-Q1 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54225-Q1 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage
to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to
the output voltage. The actual frequency may vary from 700 kHz depending on the off time, which is ended when
the fed back portion of the output voltage falls to the VFBthreshold voltage.
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 2-
μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is
2
μA.
(1)
A unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased.
When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than
feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET
gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it
coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the
initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into
regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation.
Power Good
The power good function is activated after soft start has finished. The power good function becomes active after
1.7 times soft-start time. When the output voltage is within
–10% of the target value, internal comparators detect
power good state and the power good signal becomes high. Rpg resister value, which is connected between PG
and VREG5, is required from 20 k
Ω to 150 kΩ. If the feedback voltage goes under 15% of the target value, the
power good signal becomes low after a 10 ms internal delay.
Output Discharge Control
The TPS54225-Q1 discharges the output when EN is low, or the controller is turned off by the protection
functions (OVP, UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-
MOSFET
which is connected from VO to PGND. The internal low-side MOSFET is not turned on during the output
discharge operation to avoid the possibility of causing negative voltage at the output.
Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time, and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the measured voltage is
above the voltage proportional to the current limit, then the device constantly monitors the low-side FET switch
voltage, which is proportional to the switch current, during the low-side on-time.
The converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to
the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
Copyright
2011, Texas Instruments Incorporated
7
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