- 您現在的位置：買賣IC網 > PDF目錄98282 > TPS5430MDDAREPG4 (TEXAS INSTRUMENTS INC) 8.5 A SWITCHING REGULATOR, 600 kHz SWITCHING FREQ-MAX, PDSO8 PDF資料下載
參數資料
| 型號： | TPS5430MDDAREPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 8.5 A SWITCHING REGULATOR, 600 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | GREEN, PLASTIC, SOP-8 |
| 文件頁數： | 28/28頁 |
| 文件大小： | 846K |
| 代理商： | TPS5430MDDAREPG4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁
Undervoltage Lockout (UVLO)
Boost Capacitor (BOOT)
Output Feedback (VSENSE) and Internal Compensation
Voltage Feed Forward
Feed Forward Gain +
VIN
Ramp
pk*pk
(1)
Pulse-Width Modulation (PWM) Control
Overcurrent Limiting
www.ti.com................................................................................................................................................................................................... SLVS911 – MARCH 2009
ENA has an internal pullup current source, allowing the user to float the ENA pin. If an application requires
controlling ENA, use open-drain or open-collector output logic to interface with the pin. To limit the start-up inrush
current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its final value, linearly.
The internal slow start time is 8 ms typically.
The TPS5430 incorporates a UVLO circuit to keep the device disabled when VIN (the input voltage) is below the
UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is
grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached,
the internal slow start is released and device start-up begins. The device operates until VIN falls below the UVLO
stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Connect a 0.01-
F low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, VSENSE voltage should be equal to the voltage
reference, 1.221 V.
The TPS5430 implements internal compensation to simplify the regulator design. Since the TPS5430 uses
voltage-mode control, a type-3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See Internal Compensation Network in the Advanced
Information section for more details.
The internal voltage feed forward provides a constant dc power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e,:
The typical feed-forward gain of the TPS5430 is 25.
The regulator employs a fixed-frequency PWM control method. First, the feedback voltage (VSENSE pin voltage)
is compared to the constant voltage reference by the high-gain error amplifier and compensation network to
produce a error voltage. Then, the error voltage is compared to the ramp voltage by the PWM comparator. In this
way, the error voltage magnitude is converted to a pulse width, which is the duty cycle. Finally, the PWM output
is fed into the gate-drive circuit to control the on time of the high-side MOSFET.
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain-to-source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
ignores the overcurrent indicator for the leading-edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current
limiting.
Copyright 2009, Texas Instruments Incorporated
9
Product Folder Link(s): TPS5430-EP
相關PDF資料 |
PDF描述 |
|---|---|
| TPS54310MPWPREP | 6 A SWITCHING REGULATOR, 775 kHz SWITCHING FREQ-MAX, PDSO20 |
| TPS54310PWPRG4 | 6 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO20 |
| TPS54320RHLR | SWITCHING REGULATOR, 1320 kHz SWITCHING FREQ-MAX, PQCC14 |
| TPS54320RHL | SWITCHING REGULATOR, PQCC14 |
| TPS54327DDAR | 5.7 A SWITCHING REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO8 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TPS5430-Q1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-A WIDE-INPUT-RANGE STEP-DOWN SWIFT CONVERTER |
| TPS5430QDDARQ1 | 功能描述:直流/直流開關調節器 3A Wide-Input-Range Step-Down Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS5431 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.6 MHz, 3-V TO 6-V INPUT, 3-A SYNCHRONOUS STEP-DOWN SWIFT⑩ CONVERTER WITH DISABLED SINKING DURING START-UP |
| TPS54310 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs |
| TPS54310-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V TO 6-V INPUT, 3-A OUTPUT,SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs(SWIFT?) |
發布緊急采購，3分鐘左右您將得到回復。