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參數資料
| 型號： | TPS54672PWPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 12 A SWITCHING REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數： | 4/20頁 |
| 文件大小： | 553K |
| 代理商： | TPS54672PWPG4 |
TPS54672
SLVS397C JULY 2001 REVISED FEBRUARY 2005
www.ti.com
12
2.8 V. Note that hysteresis in the UVLO comparator and a
2.5-
s rising and falling edge deglitch circuit reduce the
likelihood of shutting the device down due to noise on VIN.
Enable (ENA)
The enable pin, ENA, provides a digital control to enable
or disable (shutdown) the TPS54672. An input voltage of
1.4 V or greater ensures that the TPS54672 is enabled. An
input of 0.82 V or less ensures that device operation is
disabled. These are not standard logic thresholds, even
though they are compatible with TTL outputs.
When ENA is low, the oscillator, slow-start, PWM control
and MOSFET drivers are disabled and held in an initial
state ready for device start-up. On an ENA transition from
low to high, device start-up begins with the output starting
from 0 V.
Slow-Start
The slow-start circuit provides start-up slope control of the
output voltage to limit in-rush currents. The nominal
internal slow-start rate is 0.25 V/ms with the maximum rate
being 0.35 V/ms. When the voltage on REFIN rises faster
than the internal slope or is present when device operation
is enabled, the output rises at the internal rate. If the
reference voltage on REFIN rises more slowly, then the
output rises at about the same rate as REFIN.
VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS
pin.
X7R
or
X5R
grade
dielectrics
are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.7 V, and
that loads with ac or digital switching noise may degrade
performance. The VBIAS pin may be useful as a reference
voltage for external circuits.
Oscillator Frequency (RT)
The oscillator frequency can be set to an internally fixed
value of 350 kHz by leaving the RT pin unconnected
(floating). If a different frequency of operation is required
for the application, the oscillator frequency can be
externally adjusted from 280 kHz to 700 kHz by connecting
a resistor to the RT pin to ground. The operating frequency
is approximated by the following equation, where R is the
resistance from RT to AGND:
Switching Frequency
+ 100 kW
R
500 [kHz]
The following table summarizes the frequency selection
configurations:
FREE RUNNING FREQUENCY
RT PIN
350 kHz, internally set
Float
Externally set 280 kHz to 700 kHz
R = 68 k to 180 k
Error Amplifier (REFIN, VSENSE, COMP)
The high performance voltage error amplifier, with wide
5MHz bandwidth, low 1.5 mV-max offset, 1.4 V/
s slew
rate, and ground rail input range differentiates the
TPS54672 from most dc/dc converters. The user is given
the flexibility to use a wide range of output L and C filter
components to suit the particular application needs. Type
2 or type 3 compensation can be employed using external
compensation components.
The REFIN input range includes ground which allows 0%
duty cycle during transient conditions. The user should
note that steady state regulation accuracy of voltages less
than 0.84 V is limited by the minimum controllable ON
time.
PWM Control
Signals from the error amplifier output, oscillator and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch
and portions of the adaptive dead time and control logic
block. During steady state operation below the current limit
threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as REFIN. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54672 is capable of sinking current continuously
until the output reaches the regulation set-point.
(2)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TPS54672PWPR | 功能描述:直流/直流開關調節器 6-A Act Bus Term/DDR DC/DC Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54672PWPR | 制造商:Texas Instruments 功能描述:IC SYNC PWM SWITCHER |
| TPS54672PWPRG4 | 功能描述:直流/直流開關調節器 6-A Act Bus Term/DDR DC/DC Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54672PWRG4 | 制造商:Texas Instruments 功能描述: |
| TPS54673 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs |
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