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參數資料
| 型號： | TPS54673PWP |
| 英文描述： | SMPS Controller |
| 中文描述： | 開關電源控制器 |
| 文件頁數： | 12/16頁 |
| 文件大小： | 260K |
| 代理商： | TPS54673PWP |
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A
–
AUGUST 2001
–
REVISED JANUARY 2002
12
www.ti.com
APPLICATION INFORMATION
operating frequency
In the application circuit, 350 kHz operation is selected by leaving FSEL open. Different operating frequencies
can be selected by connecting a resistor between RT pin and AGND. Choose the value of R using equation 4
for the desired operating frequency:
R
500 kHz
SwitchingFrequency
100 k
Alternately, a preset operating frequency of 550 kHz can be selected by leaving RT open and connecting the
FSEL pin to V
I
.
output filter
The output filter is composed of a 5.2-
μ
H inductor and a 470-
μ
F capacitor. The inductor is low dc resistance
(16-m
) type, Sumida CDRH104R
–
5R2. The capacitor used is a 4-V POSCAP with a maximum ESR of 40 m
.
The output filter components work with the internal compensation network to provide a stable closed loop
response for the converter.
grounding and PowerPAD layout
The TPS54611
–
16 have two internal grounds (analog and power). Inside the TPS54611
–
16, the analog ground
ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD
is tied internally to the analog ground. Noise injected between the two grounds can degrade the performance
of the TPS54611
–
16, particularly at higher output currents. However, ground noise on an analog ground plane
can also cause problems with some of the control and bias signals. For these reasons, separate analog and
power ground planes are recommended. These two planes should tie together directly at the IC to reduce noise
between the two grounds. The only components that should tie directly to the power ground plane are the input
capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54611
–
16.
The layout of the TPS54614 evaluation module is representative of a recommended layout for a 4-layer board.
Documentation for the TPS54614 evaluation module can be found on the Texas Instruments web site
(www.ti.com) under the TPS54614 product folder. See the TPS54614
–
185 User
’
s Guide,
TI literature number
SLVU053
, and the application note,
TI literature number SLVA105
.
layout considerations for thermal performance
For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area.
A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection
from the exposes area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch
diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four
additional vias located under the device package. The size of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance
thermal performance should be included in areas not under the device package.
(4)
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