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參數(shù)資料
| 型號： | TPS56100PWPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.4 A SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數(shù)： | 26/30頁 |
| 文件大小： | 595K |
| 代理商： | TPS56100PWPR |
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TPS56100
HIGHEFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5V INPUT SYSTEMS
SLVS201A JUNE 1999 REVISED JULY 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
VREF
The reference/voltage programming (VP) section consists of a temperature-compensated bandgap reference
and a 5-bit voltage selection network. The 5 VP terminals are inputs to the VP selection network and are
TTL-compatible inputs internally pulled up to 5 V. The VP codes conform to the Intel VRM 8.3 DC-DC Converter
Specification for voltage settings between 1.8 V and 2.6 V, and they are decremented by 50 mV, down to 1.3
V, for the lower VP settings. Voltages higher than VREF can be implemented using an external resistive divider.
Refer to Table 1 for the VP code settings. The output voltage of the VP network, VREF, is within ±1.5% of the
nominal setting over the VP range of 1.3 V to 2.6 V, including a junction temperature range of 0
°C to +125°C.
The output of the reference/VP network is indirectly brought out through a buffer to the VREFB pin. The voltage
on this pin will be within 2% of VREF. It is not recommended to drive loads with VREFB, other than setting the
hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging current for
the slowstart capacitor. Refer to the slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered about VREF. The 2 external resistors form a resistor divider from VREFB
to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the comparator will be equal
to twice the voltage difference between the VREFB and VHYST pins. The propagation delay from the comparator
inputs to the driver outputs is 300 ns (maximum). The maximum hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is derived from DRV.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from DRV. The
internal bootstrap diode connected between the DRV and BOOT pins is a Schottky for improved drive efficiency.
The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver can be referenced
to ground by connecting BOOTLO to DRVGND, and connecting BOOT to a voltage supply.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FETs are on. The sampling network consists of an internal 85-
switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033
F and 0.1 F. Internal logic controls
the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur
only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.
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