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參數(shù)資料
| 型號： | TPS65150PWPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 3-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封裝： | GREEN, PLASTIC, HTSSOP-24 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 1412K |
| 代理商： | TPS65150PWPR |
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Setting the Output Voltage
Vout + 1.146 V
1 )
R1
R2
(10)
Compensation (COMP) and feedforward capacitor
C
FF +
1
2
p
z R1
+
1
2
p
8.8 kHz
R1
(11)
Layout Consideration
TPS65150
SLVS576 – SEPTEMBER 2005
The output voltage is set by the external resistor divider and is calculated as:
To minimize quiescent current high impedance feedback resistors should be used. The upper feedback resistor
R1 should not be larger than 1M
. Across the upper resistor, a bypass capacitor is required to speed up the
circuit during load transients. The capacitor value is selected according to Table 4 and the formula (12) as shown
in the next section.
The regulator loop can be compensated by adjusting the external components connected to the COMP pin. The
COMP pin is the output of the internal transconductance error amplifier. The compensation capacitor adjusts the
low-frequency gain. Adding a resistor in series to it will increase the high frequency gain. Since the converter
gain changes with the input voltage different compensation capacitors are required. Lower input voltages require
a higher gain, and therefore a smaller compensation capacitor value.
Table 4. Compensation Components for different VIN Voltages
VIN
CCOMP
RCOMP
fZ
2.5 V
470 pF
68 k
8.8 kHz
3.3 V
470 pF
33 k
7.8 kHz
5.0 V
2.2 nF
0 k
11.2 kHz
The feedforward capacitor across the feedback resistor devider of the boost converter sets an additional zero at
the frequency fz to compensate the loop. Typical values for fz are shown in Table 4 giving a feedforward
capacitor value as calculated below.
Please refer to the typical application circuits at the end of the datasheet for detailed circuit configurations and
values.
The PCB layout is an important step in the power supply design. An incorrect layout could cause converter
instability, load regulation problems, noise, and EMI issues. Especially with a switching dc-dc converter at
high load currents, too-thin PCB traces can cause significant voltage spikes. Good grounding becomes
important as well. If possible, a common ground plane to minimize ground shifts between analog (GND) and
power ground (PGND) is recommended. Additionally, the following PCB design layout guidelines are
recommended for the TPS65150:
1. Boost converter output capacitor, input capacitor and Power ground (PGND) should form a star ground or
should be directly connected together on a common power ground plane.
2. Place the input capacitor directly from the input pin (VIN) to ground.
3. Use a bold PCB trace to connect SUP to the output Vs.
4. Place a small baypass capacitor from the SUP pin to ground.
5. Use short traces for the charge-pump drive pins (DRVN, DRVP) of VGH and VGL because these traces
carry switching currents.
6. Place the charge pump flying capacitors as close as possible to the DRVP and DRVN pin, avoiding a high
voltage spikes at these pins.
7. Place the Schottky diodes as close as possible to the IC, respectively to the flying capacitors connected to
DRVP and DRVN.
8. Carfully route the chare pump traces to avoid interference with other circuits since they carry high voltage
switching currents .
9. Place the output capacitor of the VCOM buffer as close as possible to the output pin (VCOM).
19
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