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參數(shù)資料
| 型號： | TPS73215DBVTG4 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護 |
| 文件頁數(shù)： | 2/23頁 |
| 文件大小： | 663K |
| 代理商： | TPS73215DBVTG4 |
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted
(1)
POWER DISSIPATION RATINGS
(1)
TPS732xx
SBVS037I–AUGUST 2003–REVISED MAY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION
(1)
PRODUCT
TPS732
xx
yyyz
V
OUT(2)
XX
is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable
(3)
).
YYY
is package designator.
Z
is package quantity.
(1)
For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at
www.ti.com
.
Output voltages from 1.2V to 4.5V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
For fixed 1.2V operation, tie FB to OUT.
(2)
(3)
TPS732xx
–0.3 to 6.0
–0.3 to 6.0
–0.3 to 5.5
–0.3 to 6.0
Internally limited
Indefinite
See
Dissipation Ratings Table
–55 to +150
–65 to +150
2
500
UNIT
V
V
V
V
V
IN
range
V
EN
range
V
OUT
range
V
NR
, V
FB
range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, T
J
Storage temperature range
ESD rating, HBM
ESD rating, CDM
°
C
°
C
kV
V
(1)
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
DERATING FACTOR
ABOVE T
A
= 25
°
C
3.9mW/
°
C
5.6mW/
°
C
18.9mW/
°
C
25.0mW/
°
C
T
≤
25
°
C
POWER RATING
390mW
560mW
1.89W
2.50W
T
= 70
°
C
POWER RATING
215mW
310mW
1.04W
1.38W
T
= 85
°
C
POWER RATING
155mW
225mW
0.76W
1.0W
BOARD
PACKAGE
R
Θ
JC
R
Θ
JA
Low-K
(2)
High-K
(3)
Low-K
(2)
High-K
(3)(4)
DBV
DBV
DCQ
DRB
64
°
C/W
64
°
C/W
15
°
C/W
1.2
°
C/W
255
°
C/W
180
°
C/W
53
°
C/W
40°C/W
(1)
(2)
See
Power Dissipation
in the
Applications
section for more information related to thermal design.
The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
Based on preliminary thermal simulations.
(3)
(4)
2
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