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參數(shù)資料
| 型號(hào)： | TPS73230DCQ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無(wú)電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大?。?/td> | 427K |
| 代理商： | TPS73230DCQ |
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DROPOUT VOLTAGE
The TPS732xx uses an NMOS pass transistor to
achieve extremely low dropout. When (V
- V
) is
less than the dropout voltage (V
DO
), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the R
DS-ON
of the NMOS
pass element.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the PCB be designed with separate ground planes for
V
IN
and V
OUT
, with each ground plane connected only
at the GND pin of the device. In addition, the ground
connection for the bypass capacitor should connect
directly to the GND pin of the device.
TRANSIENT RESPONSE
The low open-loop output impedance provided by the
NMOS pass element in a voltage follower configur-
ation allows operation without an output capacitor for
many applications. As with any regulator, the addition
of a capacitor (nominal value 1μF) from the output pin
to ground will reduce undershoot magnitude but
increase duration. In the adjustable version, the
addition of a capacitor, C
FB
, from the output to the
adjust pin will also improve the transient response.
INTERNAL CURRENT LIMIT
The TPS732xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
V
OUT
drops below 0.5V. See Figure 11 in the Typical
Characteristics section for a graph of I
OUT
vs V
OUT
.
SHUTDOWN
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. V
below 0.5V (max)
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown capa-
bility is not required, the Enable pin can be connected
to V
IN
. When a pull-up resistor is used, and operation
down to 1.8V is required, use pull-up resistor values
below 50 k
.
dV dt
V
OUT
C
OUT
80k
(4)
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
This noise reduction effect is shown as
RMS Noise
Voltage vs C
NR
in the Typical Characteristics section.
The TPS73201 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, C
FB
, from the output to the FB pin
will reduce output noise and improve load transient
performance.
The TPS732xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above V
OUT
. The
charge pump generates ~250μV of switching noise at
~2MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
values of I
OUT
and C
OUT
.
For large step changes in load current, the TPS732xx
requires a larger voltage drop from V
to V
to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of V
- V
OUT
above this line
insure normal transient response.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available head-
room (V
IN
to V
OUT
voltage drop). Under worst-case
conditions [full-scale instantaneous load change with
(V
- V
) close to dc dropout levels], the TPS732xx
can take a couple of hundred microseconds to return
to the specified regulation accuracy.
The TPS732xx does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as alter-
nate power supplies, to the output. This also results
in an output overshoot of several percent if the load
current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor C
OUT
and the internal/external load resist-
ance. The rate of decay is given by:
(Fixed voltage version)
13
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TPS73230DCQG4 | 功能描述:低壓差穩(wěn)壓器 - LDO Cap-Free NMOS 250mA RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類(lèi)型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TPS73230DCQR | 功能描述:低壓差穩(wěn)壓器 - LDO Cap-Free NMOS 250mA RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類(lèi)型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TPS73230DCQRG4 | 功能描述:低壓差穩(wěn)壓器 - LDO Cap-Free NMOS 250mA RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類(lèi)型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TPS73230MDBVREP | 功能描述:低壓差穩(wěn)壓器 - LDO Mil Enh Cap-Free NMOS 250-mA LDO Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類(lèi)型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TPS73233DBVR | 功能描述:低壓差穩(wěn)壓器 - LDO Cap-Free NMOS 250mA RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類(lèi)型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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