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參數資料
| 型號： | TPS92001DGKR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | FLUORESCENT LIGHT CONTROLLER, 110 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | GREEN, PLASTIC, MSOP-8 |
| 文件頁數： | 17/19頁 |
| 文件大小： | 917K |
| 代理商： | TPS92001DGKR |
C
CT
S
OSC
Q
OSC
=CLK=S
PWM
CS
R
PWM
Q
PWM
V
GD
C
CT
Charging
C
CT
Discharging
3.33 V
1.67 V
1 V
70%
ON
30%
OFF
CS Signal Dominant
Maximum Duty Cycle Dominant
R
OSC
UDG-10006
www.ti.com
SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
Figure 2. Oscillator Latch and PWM Latch Waveforms
Figure 2 shows the waveforms associated with the oscillator latch and the PWM latch (shown in the Typical
Application Diagram). A high CLK signal not only initiates a discharge cycle for CCT, it also turns on the internal
N-channel MOSFET on the CS pin causing any external capacitance used for leading edge blanking connected
to this pin to be discharged to ground. By discharging any external capacitor completely to ground during the
external switch off-time, the noise immunity of the converter is enhanced allowing the user to design in smaller
R-C components for leading edge blanking. A high CLK signal also sets the level sensitive S input of the PWM
latch, SPWM, high, resulting in a high output, QPWM, as shown in Figure 2. This QPWM signal remains high until a
reset signal, RPWM is received. A high RPWM signal results from the CS signal crossing the 1-V threshold, or
during soft-start or if the SS pin is disabled.
Assuming the UVLO threshold is satisfied, the GD signal of the device remains high as long as QPWM is high and
SPWM, also referred to as CLK, is low. The GD signal is dominated by the CS signal as long as the CS signal
trips the 1-V threshold while CLK is low. If the CS signal does not cross the 1-V threshold while CLK is low, the
GD signal will be dominated by the maximum duty cycle programmed by the user. Figure 2 illustrates the various
waveforms for a design set up for a maximum duty cycle of 70%.
The recommended value for CCT is 1 nF for frequencies in the 100 kHz or less range and smaller CCT for higher
frequencies. The minimum recommended values of RRTC is 10 kΩ. The minimum recommended value of RRTD is
4.32 k
Ω. Using these values maintains a ratio of at least 20:1 between the RDS(on) of the internal FETs and the
external timing resistors, resulting in minimal change in frequency over temperature. Because of the oscillator
susceptibility to capacitive coupling, examine the oscillator frequency by looking at the common RTC-RTD-CT
node on the circuit board as opposed to looking at pins 3 and 4 directly. For good noise immunity, the RTC and
RTD resistors should be placed as close to pins 3 and 4 of the device as possible. The timing capacitor should
be returned directly to the ground pin of the device with minimal stray inductance and capacitance.
Copyright 2010, Texas Instruments Incorporated
7
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