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參數資料
| 型號： | TPU3040PK |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 圖文 |
| 英文描述： | TELETEXT DECODER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數： | 21/72頁 |
| 文件大小： | 576K |
| 代理商： | TPU3040PK |
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PRELIMINARY DATA SHEET
TPU 3035, TPU 3040, TPU 3050
MICRONAS INTERMETALL
28
4.2.1.1. CPU Subaddressing
There are 2 CPU subaddresses to access CPU
memory: either with static memory address or with auto-
incrementing memory address. The main purpose of
CPU subaddressing is to write text into the OSD buffer
and to access the I/O page (see chapter 4.15.). The stat-
ic CPU subaddress can be used to write more than 1
byte into the same I/O page register.
The CPU subaddress has to be followed by 2 address
bytes defining the CPU memory address. The following
data byte is written into this address. In the case of auto-
increment the continuation bytes are written into incre-
menting memory addresses.
The CPU telegram can be stopped after the 2 memory
address bytes. The following I2C telegram subaddres-
sing the data register will continue data transfer to or
from the CPU memory. The data transfer will always
start at the CPU memory address (autoincrement is not
saved).
< 22 78 ah al dd .. >
< 22 79 ah al dd .. >
< 22 79 ah al
> <
22 7C dd .. >
Data is directly written into CPU memory without using
the I2C buffer of TPU 3040 and without waiting for a stop
condition.
4.2.1.2. DRAM Subaddressing
DRAM access is necessary to generate level 2 displays.
The external DRAM can be addressed on byte level. The
maximum DRAM size of 16 Mbit requires a 21-bit
memory address pointer. The format of the DRAM ad-
dress pointer is shown in Fig. 4–2.
5-bit Bank
8-bit High
8-bit Low
Fig. 4–2: DRAM Address Pointer
The DRAM subaddress has to be followed by 3 address
bytes defining the DRAM address pointer. The following
data byte is written into this address.
DRAM subaddressing always uses autoincrement. Sep-
arate read and write DRAM address pointers are saved
for autoincrement.
The DRAM telegram can be stopped after the 3 address
pointer bytes. The following I2C telegram subaddressing
the data register will continue data transfer to or from the
DRAM.
When reading the DRAM, the first data byte the TPU
3040 returns is a dummy byte, which has to be ignored.
< 22 7A ab ah al dd .. >
< 22 7A ab ah al
> < 22 7C dd .. >
< 22 7A ab ah al
> < 22 7C <
23 dd ..>
Data written to the DRAM subaddress is collected first
in the I2C buffer of TPU 3040 and is copied to DRAM
when the buffer is full (48 bytes) or after stop condition.
During the time the buffer is copied to DRAM the TPU
3040 will hold the I2C clock line down.
Reading data from the DRAM subaddress is also buff-
ered internally. Reading the first byte will only empty the
I2C buffer. Every time the buffer is empty, the TPU 3040
will copy 48 bytes from DRAM into the I2C buffer. During
this time the TPU 3040 will hold the I2C clock line down.
4.2.1.3. Command Subaddressing
TPU 3040 supports a command language, allowing the
host controller to start complex processing inside the
TPU 3040 with simple commands (see chapter 4.9.).
Commands have to be sent to the command subad-
dress.
The command subaddress has to be followed by the
command code. The following data bytes are taken as
command parameters.
The execution time for commands depends on other
processes running inside the TPU 3040 firmware, there-
fore the host controller has to read the status register to
get information about the running command before
reading command parameter or starting other com-
mands.
The status register returns information about the com-
mand interface. The ‘command wait’ bit is set during
execution of a command and is reset when a command
is executed completely and read parameters are avail-
able. If a non-existing command is sent to the TPU 3040,
the ‘command invalid’ bit is set. If a command could not
be executed successfully, the ‘command found no data’
bit is set. In this case the read parameters of this com-
mand are not valid.
Reading status from TPU 3040 is done by subaddres-
sing the status register followed by repeated start condi-
tion and slave read address (see Fig. 4–3).
< 22 7B cc dd ..
>
< 22 7D <
23 ss .. >
< 22 7C <
23 dd .. >
Telegrams subaddressing the command interface are
buffered and processed after receiving the stop condi-
tion. Therefore the command code and all necessary
command parameters have to be included in a single
telegram.
相關PDF資料 |
PDF描述 |
|---|---|
| TPU3040PO | TELETEXT DECODER, PDIP52 |
| TPU3040PQ | TELETEXT DECODER, PQCC44 |
| TPU3050PO | TELETEXT DECODER, PDIP52 |
| TQ6122-D | PARALLEL, 8 BITS INPUT LOADING, 0.002 us SETTLING TIME, 8-BIT DAC, UUC60 |
| TQ6122-M | PARALLEL, 8 BITS INPUT LOADING, 0.002 us SETTLING TIME, 8-BIT DAC, CQFP44 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TPU3041 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Cyrillic/Greek Teletext Processor |
| TPU3042 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| TPU305 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | JFET | P-CHANNEL | 15MA I(DSS) | TO-226AA |
| TPU3050(PDIP40) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| TPU3050(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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