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參數資料
| 型號： | TPU3040PO |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 圖文 |
| 英文描述： | TELETEXT DECODER, PDIP52 |
| 封裝： | SHRINK, PLASTIC, DIP-52 |
| 文件頁數： | 72/72頁 |
| 文件大小： | 576K |
| 代理商： | TPU3040PO |
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TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
9
Full Screen Layer
WST Layer
OSD Layer
Fig. 2–3: Display Layer
2.8. DRAM Interface
The DRAM interface connects a standard DRAM to the
internal bus structure. The address bus is 12 bit wide,
addressing DRAMs up to 16 Mbit. Smaller DRAMs can
also be connected. The maximum data throughput of the
DRAM interface is 8.82 Mbit/s. This fast mode timing is
adapted to DRAMS with page mode cycle time faster
than 85 ns. In slow mode the data rate is 6.1 Mbit/s and
the timing is adapted to DRAMS with a page mode cycle
time faster than 120 ns. The data rate calculation al-
ready takes into account the required refresh cycles.
The DRAM interface has to handle 3 asynchronous data
streams. The CPU needs access to every memory loca-
tion of the DRAM. During VBI the slicer writes up to 22
teletext lines of 43 bytes into the acquisition scratch
memory. Alternatively the slicer can store MAC packets
of 90 bytes into the acquisition scratch. During text dis-
play the display controller copies teletext rows from dis-
play memory into its internal row buffer.
The lower data rate of the slow mode makes some re-
strictions necessary. With 6.1 Mbit/s it is no longer possi-
ble to run slicer and display in parallel. Only MAC packet
teletext can still be acquired asynchronously because of
the lower bit rate. VBI teletext can only be acquired while
the display controller is inactive (synchronous acquisi-
tion and display).
2.9. SRAM Interface
The TPU 3050 is able to address either DRAM or SRAM
memories. The DRAM interface can be switched into
SRAM mode via I2C-Bus. The SRAM interface is in-
serted between the DRAM interface and the actual
memory and demultiplexes the DRAM addresses into a
single SRAM address and arranges the serial DRAM
data into parallel data. Therefore, there is no gain in
speed when SRAM is connected and slow SRAM types
(100 ns) can be used. The internal, as well as the exter-
nal controller software, does not see any difference be-
tween DRAM and SRAM mode.
2.10. Applications
The field of applications covers analog and digital TV
sets, set-top satellite decoders, video recorders and
home computers. For example, Fig. 2–4 shows how the
TPU 3040 fits into an analog environment. Two analog
sources are connected and the output is analog RGB,
synchronized with an external sync signal or self-timed.
Page selection and other user actions are sent to the
TPU 3040 via I2C-Bus using a high level command lan-
guage.
Tuner 1
Tuner 2
DRAM
R
G
B
Sync
I2C-Bus
TPU 3040
Fig. 2–4: Stand-Alone Application
Controller
相關PDF資料 |
PDF描述 |
|---|---|
| TPU3040PQ | TELETEXT DECODER, PQCC44 |
| TPU3050PO | TELETEXT DECODER, PDIP52 |
| TQ6122-D | PARALLEL, 8 BITS INPUT LOADING, 0.002 us SETTLING TIME, 8-BIT DAC, UUC60 |
| TQ6122-M | PARALLEL, 8 BITS INPUT LOADING, 0.002 us SETTLING TIME, 8-BIT DAC, CQFP44 |
| TRC1300N | RF, REMOTE CONTROL SUPPORT CIRCUIT, PDIP16 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TPU3041 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Cyrillic/Greek Teletext Processor |
| TPU3042 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| TPU305 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | JFET | P-CHANNEL | 15MA I(DSS) | TO-226AA |
| TPU3050(PDIP40) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| TPU3050(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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