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參數資料
| 型號： | TS(X)8387MFB/C |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 20/38頁 |
| 文件大小： | 617K |
| 代理商： | TS(X)8387MFB/C |
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TS8387
27/38
7.3.
CLOCK INPUTS (CLK) (CLKB)
7.3.1.DIFFERENTIAL ECL CLOCKS INPUTS
The ADC clock input buffer is a differential preamplifier stage, which has been designed in order to be used either in
differential or single-ended mode.
The clock inputs were intended to be driven differentially with nominal –0.8V / –1.8V ECL levels.
In this mode, a low phase noise sinewave generator can be used for driving the clock inputs, followed by a power splitter
( hybrid junction ) in order to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offseting
the common mode voltage to ECL levels.
Note : As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the
signals to be 180 degrees out of phase.
Differential Clock inputs (ECL Levels)
–0.8V
[mV]
t
–1.8V
VCLKB
VCLK
Common mode = –1.3 V
7.3.2.SINGLE ENDED ECL CLOCK INPUT
The TS8387 can be clocked at full speed without noticeable performance degradation in either differential or single
ended configuration, using clock input ECL levels.
This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed
in order to be entered either in differential or single-ended mode.
This is true so long as the out of phase clock input pad is 50 ohms terminated very closely to one of the neighbouring
shield ground pad, which acts as the local Ground reference for the inphase clock input .
In single-ended configuration enter on CLK ( resp. CLKB ) pad , with the inverted phase Clock input pad CLKB (resp.
CLK) grounded.
The inphase input amplitude is 1 Volt peak to peak, centered on –1.3 Volt common mode.
The inverted phase clock input is grounded through the 50 ohms termination resistor.
Single ended Clock input (ECL):
VCLK common mode = –1.3 Volt.
VCLKB = –1.3 Volt
–0.8V
[V]
t
–1.8V
VCLK
VCLKB = –1.3 V
CLK or CLKB
CLK or CLKB double pad
50
(external)
50
reverse termination
1M
0.4 pF
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