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參數資料
| 型號： | TS(X)8387MFDSSC/SMD |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 37/38頁 |
| 文件大小： | 617K |
| 代理商： | TS(X)8387MFDSSC/SMD |
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TS8387
8/38
Test
level
Unit
Max
Typ
Min
Temp
Symb
Parameter
Two tone intermodulation distortion
(note 2)
IMD
FIN1 = 199 MHz @ FS=500 MSPS
–53
dBc
FIN2 = 200 MHz @ FS=500 MSPS
SWITCHING PERFORMANCE AND CHARACTERISTICS
- See Timing Diagrams Figure 1
Maximum clock frequency
FS
500
MSPS
Minimum clock frequency
FS
IV
10
MSPS
Minimum Clock pulse width (high)
TC1
IV
0.8
1
50
ns
Minimum Clock pulse width (low)
TC2
IV
0.8
1
50
ns
Aperture delay
(Note 2)
TA
IV
0
ns
Aperture uncertainty
(Notes 2, 5)
(differential clock inputs)
Jitter
IV
1
ps
(rms)
Data output delay
(Notes 2, 9, 10, 11)
TOD
Full
IV
900
1100
1400
ps
Output rise time (20 % - 80 % )-
(note 10)
Output fall time (20%–80 %) for DATAs
TR/TF
Full
IV
400
500
700
ps
Output rise time (20 % – 80 %)
Output fall time (20 % - 80 % ) -
(note 10)
for Data ready
TR/TF
Full
IV
200
300
500
ps
Data ready output delay
(Notes 2, 9, 10, 11)
TDR
Full
IV
800
1000
1300
ps
(Notes 12)
. . . . . . . . . .
TOD–
TDR
Full
IV
100
ps
(Note 2)
(Note 8)
TD
Full
IV
800
900
1000
ps
Data pipeline delay
TPD
IV
2.5
clock
cycles
Note 1 : Differential output buffers are internally loaded by 75
W resistors. Buffer bias current = 11 mA.
Note 2 : See definition of terms
Note 3 : Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS.
Note 4 : Output error amplitude < +/– 4 LSB around worst code.
Note 5 : Maximum jitter value obtained for single-ended clock input.
Note 6 : Digital outputs back termination options depicted in Advanced Application Notes figures 3,4,5 .
Note 7:The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level into
the 50
W termination resistor of the inphase clock input. (4 dBm into 50 W clock input correspond to 10 dBm power level for the
clock generator.)
Note 8 :TDR–TOD = – 100 ps (typ) does not depend on the sampling rate.
eg : at 500 Msps and 50/50 clock duty cycle : TC2 = 1000 ps (=TC1) and TDR – TOD =– 100 ps (TC1+TC2 = 1 = clock period)
Note 9 : Specified loading conditions for digital outputs :
– 50 ohms or 75 ohms controlled impedance traces properly 50 / 75 ohms terminated, or unterminated 75 ohms controlled
impedance traces.
– Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola.
( e.g. : 10E452 ) ( Typical input parasitic capacitance of 1.5 pF including package and ESD protections. )
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