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參數資料
| 型號： | TS(X)8387VF_ |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | 24 X 24 MM, CERAMIC, QFP-68 |
| 文件頁數： | 38/38頁 |
| 文件大小： | 617K |
| 代理商： | TS(X)8387VF_ |
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TS8387
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Note 10 : Termination load parasitic capacitance derating values :
– 50 ohms or 75 ohms controlled impedance traces properly 50 / 75 ohms terminated : 60 ps / pF or 75 ps per additionnal
ECLinPS load.
– Unterminated ( source terminated ) 75 ohms controlled impedance lines : 100 ps / pF or 150 ps per additionnal ECLinPS
termination load.
Note 11 :apply proper 50 / 75 impedance traces propagation time derating values:
6 ps / mm (155 ps/inch) for TSEV8387 Evaluation Board.
Note 12 : Values for TOD and TDR track each other over temperature, ( 1 percent variation for TOD – TDR per 100 degrees Celsius
temperature variation ). Therefore TOD – TDR variation over temperature is negligible. Moreover, the internal ( onchip ) and
package skews between each Data TODs and TDR effect can be considered as negligible.Consequently, minimum values
for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced
Application Notes about TOD – TDR variation over temperature in section 7).
TC1
TC2
DATA N
CLK
TA
X
N+1
X
N+2
X
N+3
PIPELINE DELAY (TPD) : 2.5 CLOCK PERIODS
N
VIN
Figure 1 : TS8387 TIMING DIAGRAM
DATA READY
OUTPUT
DATA N–1
TDR
DIGITAL
OUTPUTS
TOD
DATA N–2
TS8387 principle of operation :
The analog input is sampled on the rising edge of external clock input (CLK,CLKB) after TA (aperture delay) of typically 0
ps .
The digitized data is available after 2.5 clock periods latency (pipeline delay (TPD)), on clock falling edge, after 1100 ps
typical propagation delay TOD.
The Data Ready differential output signal (DR,DRB) switches at external clock frequency, that is at twice the digital
output data rate .
The Data Ready output signal (DR,DRB) switches on external clock falling edge after a propagation delay TDR of typi-
cally 1000 ps.
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