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參數資料
| 型號： | TS(X)8387VF_ |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 21/38頁 |
| 文件大小： | 617K |
| 代理商： | TS(X)8387VF_ |
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TS8387
28/38
7.3.3.SINGLE ENDED CLOCK INPUT (Ground Common Mode)
An even more convenient clock input configuration is proposed below :
The TS8387 clock buffer can also manage a single-ended sinewave clock signal centered around 0 Volt.
(out of phase clock signal grounded through the 50 Ohm termination resistor).
The typical inphase clock input amplitude is 1 Volt peak to peak, centered on 0 Volt (ground) common mode.
This corresponds to a typical clock input power level of 4 dBm into the 50 ohms termination resistor.
Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors.
The inverted phase clock input is grounded through the 50 ohms termination resistor.
Single ended Clock input (Ground common mode)
VCLK common mode = 0 Volt
VCLKB=0 Volt
4 dBm typical clock input power level
(into 50 ohms termination resistor)
[V]
t
VCLK
VCLKB = ( 0 V )
–0.5V
+0.5V
Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level.
7.4.
CLOCK SIGNAL DUTY CYCLE ADJUST
In single ended configuration, when using a sinewave clock generator,the clock signal duty cycle can be easily adjusted
by simply offseting the inphase clock signal using a biasing tee, (as the out of phase clock input is at ground level ).
Single ended Clock input (Inphase clock input common mode shifted)
VCLK common mode = –180mV
VCLKB = 0 Volt
[V]
t
VCLK – 180 mV
VCLKB = ( 0 V )
–0.5V
40 %
60 %
+0.5V
Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level.
Note 2 :For an input CLK signal of 4 dBm into 50 ohms, the typical offset value to achieve a 40 / 60 clock duty cycle is –180 mV on
CLK.
7.5.
NOISE IMMUNITY INFORMATIONS
Circuit noise immunity performance begins at design level.
Efforts have been made on the design in order to make the device as insensitive as possible to chip environment per-
turbations resulting from the circuit itself or induced by external circuitry.
(Cascode stages isolation, internal damping resistors, clamps, internal (onchip) decoupling capacitors.)
Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immu-
nity by common mode noise rejection.
Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced
differential amplifiers.
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