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參數資料
| 型號： | TS(X)PC603PVAU/T6ME |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CERQUAD-240 |
| 文件頁數： | 1/38頁 |
| 文件大小： | 704K |
| 代理商： | TS(X)PC603PVAU/T6ME |
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June 1998
DESCRIPTION
The PID7v-603e implementation of PowerPC603e (after
named 603p) is a low-power implementation of reduced
instruction set computer (RISC) microprocessors PowerPC
family. The 603p implements 32-bit effective addresses, inte-
ger data types of 8, 16 and 32 bits, and floating-point data types
of 32 and 64 bits.
The 603p is a low-power 2.5/3.3-volt design and provides four
software controllable power-saving modes.
The 603p is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions
can execute out of order for increased performance ; however,
the 603p makes completion appear sequential. The 603p inte-
grates five execution units and is able to execute five instruc-
tions in parallel.
The 603p provides independent on-chip, 16-Kbyte, four-way
set-associative, physically addressed caches for instructions
and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-
associative, data and instruction translation lookaside buffers
that provide support for demand-paged virtual memory
address translation and variable-sized block translation.
The 603p has a selectable 32 or 64-bit data bus and a 32-bit
address bus. The 603p interface protocol allows multiple mas-
ters to complete for system resources through a central exter-
nal arbiter. The 603p supports single-beat and burst data
transfers for memory accesses, and supports memory-
mapped I/O.
The 603p uses an advanced, 2.5/3.3-V CMOS process tech-
nology and maintains full interface compatibility with TTL devi-
ces.
The 603p integrates in system testability and debugging fea-
tures through JTAG boundary-scan capability.
MAIN FEATURES
H 4.0 SPECint95, 5.3 SPECfp95 @ 166 MHz (estimated)
H Superscalar (3 instructions per clock peak).
H Dual 16KB caches.
H Selectable bus clock.
H 32-bit compatibility PowerPC implementation.
H On chip debug support.
H PD typical = 3.0 Watts (166 MHz), full operating conditions.
H Nap, doze and sleep modes for power savings.
H Branch folding.
H 64-bit data bus (32-bit data bus option).
H 4-Gbyte direct addressing range.
H Pipelined single/double precision float unit.
IEEE 754 compatible FPU.
H IEEE P 1149-1 test mode (JTAG/C0P).
H fint max = 166 MHz. (200 MHz planned).
H fbus max = 66.67 MHz.
H Compatible CMOS input / TTL Output.
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
G suffix
CBGA 255
Ceramic Ball Grid Array
(To be introduced)
CERQUAD 240
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with :
H MIL-STD-883 class B or According to TCS standards
(planned)
H Upscreenings based upon TCS standards
H Full military temperature range (Tc = -55°C, Tc= +125°C)
Industrial temperature range
(Tc = –40°C, Tc= +110°C)
H Internal // I/O Power Supply = 2.5 ± 5 % // 3.3 V ± 5 %.
H 240 pin Cerquad or 255 pin CBGA packages
TSPC603p
PowerPC 603e
RISC MICROPROCESSOR Family
PID7v-603e Specification
相關PDF資料 |
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|---|---|
| TSPC603PMAB/C8LE | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| TSPC603PMAB/C8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| TSPC603PMAB/T8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| TSPC603PVA8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| TS(X)PC603PMA6ME | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
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