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參數資料
| 型號： | TS3L500AERUAR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | OCTAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, QCC42 |
| 封裝： | QFN-42 |
| 文件頁數： | 16/17頁 |
| 文件大小： | 480K |
| 代理商： | TS3L500AERUAR |
PARAMETER MEASUREMENT INFORMATION
CL
(see Note A)
TEST CIRCUIT
S1
2
× VCC
Open
GND
RL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
50
VG1
VCC
DUT
50
VIN
50
VG2
50
VI
TEST
RL
S1
V
CL
VCC
Vin
tPLZ/tPZL
3.3 V
± 0.3 V
2
× VCC
200
GND
10 pF
0.3 V
Input Generator
VO
tPHZ/tPZH
3.3 V
± 0.3 V
GND
200
VCC
10 pF
0.3 V
tPZL
VOH 0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
Output Control
(VIN)
1.25 V
2.5 V
VOH
VOL + 0.3 V
VOH
VOL
0 V
1.25 V
tPZH
tPLZ
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
Output
Waveform 1
S1 at 2 y VCC
(see Note B)
VOL
VO
VI
VO
SCDS246A – JUNE 2007 – REVISED AUGUST 2008 ....................................................................................................................................................... www.ti.com
(Enable and Disable Times)
Figure 5. Test Circuit and Voltage Waveforms
8
Copyright 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TS3L500AE
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