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參數資料
| 型號： | TS4851IJT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PBGA18 |
| 封裝： | FCP-18 |
| 文件頁數： | 27/28頁 |
| 文件大小： | 1280K |
| 代理商： | TS4851IJT |
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TS4851
Electrical Characteristics
8/28
Table 9.
Electrical characteristics at VCC = +3V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
ICC
Supply Current
Output Mode 7, Vin = 0V,no load
All other output modes, Vin = 0V,no load
7.5
4.5
10
6.5
mA
ISTANDBY
Standby Current
Output Mode 0
0.1
2
A
Voo
Output Offset Voltage (differential)
Vin = 0V
5
50
mV
Vil
“Logic low” input Voltage
0
0.4
V
Vih
“Logic high” input Voltage
1.4
5
V
Po
Output Power
SPKERout, RL = 8
, THD = 1%, F = 1kHz
Rout & Lout, RL = 32
, THD = 0.5%, F = 1kHz
300
20
340
30
mW
THD + N
Total Harmonic Distortion + Noise
Rout & Lout, Po = 20mW, F = 1kHz, RL = 32
SPKERout, Po = 300mW, F = 1kHz, RL = 8
Rout & Lout, Po = 15mW, 20Hz < F < 20kHz, RL = 32
SPKERout, Po = 250mW, 20Hz < F < 20kHz, RL = 8
0.5
1
0.5
1
%
SNR
Signal To Noise Ratio (A-Weighted)
86
dB
PSRR1
Power Supply Rejection Ratio2
Vripple = 200mV Vpp, F = 217Hz, Input(s) Terminated 10
Ouput Mode 1
Ouput Mode 2
Ouput Mode 3 (G=+12dB)
Ouput Mode 4 (G=+12dB)
Ouput Mode 5 (G=+12dB)
Ouput Mode 6, 7 (G=+12dB)
65
70
54
51
53
dB
G
Digital Gain Range - Rin & Lin
no load
-34.5
-
+12
dB
Digital gain stepsize
1.5
dB
Stepsize error
G
≥ -22.5dB
G < -22.5dB
-0.5
-1
+0.5
+1
dB
Phone In Gain, no load
BTL gain from Phone In to SPKERout
BTL gain from Phone In to Rout & Lout
6
0
dB
Zin
Phone In Input Impedance 1
15
20
25
k
Zin
Rin & Lin Input Impedance (All Gain Setting) 1
37.5
50
62.5
k
tes
Enable Stepup Time - ENB
20
ns
teh
Enable Hold Time - ENB
20
ns
tel
Enable Low Time - ENB
30
ns
tds
Data Setup Time- DATA
20
ns
tdh
Data Hold Time - DATA
20
ns
tcs
Clock Setup time - CLK
20
ns
tch
Clock Logic High Time - CLK
50
ns
tcl
Clock Logic Low Time - CLK
50
ns
fclk
Clock Frequency - CLK
DC
10
MHz
1)
All PSRR data limits are guaranted by evaluation desgin test.
2)
Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217Hz
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相關代理商/技術參數 |
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| TS4855 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOUDSPEAKER & HEADSET DRIVER WITH VOLUME CONTROL |
| TS4855_04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOUDSPEAKER & HEADSET DRIVER WITH VOLUME CONTROL |
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