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參數資料
| 型號： | TS80C188EC13 |
| 英文描述： | MICROPROCESSOR|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 微處理器| 16位|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數： | 29/57頁 |
| 文件大小： | 585K |
| 代理商： | TS80C188EC13 |
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80C186EC/188EC, 80L186EC/188EC
I
CC
versus Frequency and Voltage
The I
CC
consumed by the processor is composed of
two components:
1. I
PD
DThe quiescent current that represents inter-
nal device leakage. Measured with all inputs at
either V
CC
or ground and no clock applied.
2. I
CCS
DThe switching current used to charge and
discharge internal parasitic capacitance when
changing logic levels. I
CCS
is related to both the
frequency of operation and the device supply
voltage (V
CC
). I
CCS
is given by the formula:
Power
e
V
*
I
e
V
2
*
C
DEV
*
f
...
I
CCS
e
V
*
C
DEV
*
f
Where:
V
e
Supply Voltage (V
CC
)
C
DEV
e
Device Capacitance
f
e
Operating Frequency
Measuring C
PD
on a device like the 80C186EC
would be difficult. Instead, C
PD
is calculated using
the above formula with I
CC
values measured at
known V
CC
and frequency. Using the C
PD
value, the
user can calculate I
CC
at any voltage and frequency
within the specified operating range.
Example.
Calculate typical I
CC
at 14 MHz, 5.2V V
CC
.
I
CC
e
I
PD
a
I
CCS
e
0.1 mA
a
5.2V
*
0.77
*
14 MHz
e
56.2 mA
PDTMR Pin Delay Calculation
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown Mode. A delay is
required only when using the on chip oscillator to
allow the crystal or resonator circuit to stabilize.
NOTE:
The PDTMR pin function does not apply when
RESIN is asserted (i.e. a device reset while in Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabilized.
To calculate the value of capacitor to use to provide
a desired delay, use the equation:
440
c
t
e
C
PD
(5V, 25
§
C)
Where:
t
e
desired delay in
seconds
C
PD
e
capacitive load on PDTMR in
microfarads
Example.
For a delay of 300
m
s, a capacitor value of
C
PD
e
440
c
(300
c
10
b
6
e
0.132
m
F is required.
Round up to a standard (available) capacitor value.
NOTE:
The above equation applies to delay time longer
than 10
m
s and will compute the
TYPICAL
capaci-
tance needed to achieve the desired delay. A delay
variance of
a
50% to
b
25% can occur due to
temperature,
voltage,
and
tremes. In general, higher V
CC
and/or lower tem-
peratures will decrease delay time, while lower V
CC
and/or higher temperature will increase delay time.
device
process
ex-
Parameter
Typical
Max
Units
Notes
CPD
0.77
1.37
mA/V
*
MHz
1, 2
CPD (Idle Mode)
0.55
0.96
mA/V
*
MHz
1, 2
NOTES:
1. Maximum C
is measured at
b
40
§
C with all outputs loaded as specified in the AC test conditions and the device in reset
(or Idle Mode). Due to tester limitations, CLKOUT and OSCOUT also have 50 pF loads that increase I
CC
by V
*
C
*
F.
2. Typical C
PD
is calculated at 25
§
C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode).
29
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相關代理商/技術參數 |
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