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參數資料
| 型號： | TS80C188EC20 |
| 元件分類： | 微處理器 |
| 英文描述： | MICROPROCESSOR|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 微處理器| 16位|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數： | 9/57頁 |
| 文件大小： | 585K |
| 代理商： | TS80C188EC20 |
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80C186EC/188EC, 80L186EC/188EC
Column 4: Output States (for O and I/O types
only)
The state of an output or I/O pin is de-
pendent on the operating mode of the
device. There are four modes of opera-
tion that are different from normal active
mode: Bus Hold, Reset, Idle Mode, Pow-
erdown Mode. This column describes
the output pin state in each of these
modes.
The legend for interpreting the information in the Pin
Descriptions is shown in Table 1.
As an example, please refer to the table entry for
AD12:0. The ‘‘I/O’’ signifies that the pins are bidirec-
tional (i.e. have both an input and output function).
The ‘‘S’’ indicates that, as an input the signal must
be synchronized to CLKOUT for proper operation.
The ‘‘H(Z)’’ indicates that these pins will float while
the processor is in the Hold Acknowledge state.
R(Z) indicates that these pins will float while RESIN
is low. P(0) and I(0) indicate that these pins will drive
0 when the device is in either Powerdown or Idle
Mode.
Some pins, the I/O Ports for example, can be pro-
grammed to perform more than one function. Multi-
function pins have a ‘‘/’’ in their signal name be-
tween the different functions (i.e. P3.0/RXI1). If the
input pin type or output pin state differ between func-
tions, then that will be indicated by separating the
state (or type) with a ‘‘/’’ (i.e. H(X)/H(Q)). In this
example when the pin is configured as P3.0 then its
hold output state is H(X); when configured as RXI1
its output state is H(Q).
All pins float while the processor is in the ONCE
Mode (with the exception of OSCOUT).
Table 1. Pin Description Nomenclature
Symbol
Description
P
G
I
O
I/O
Power Pin (apply
a
V
CC
voltage)
Ground (connect to V
SS
)
Input only pin
Output only pin
Input/Output pin
S(E)
S(L)
A(E)
A(L)
Synchronous, edge sensitive
Synchronous, level sensitive
Asynchronous, edge sensitive
Asynchronous, level sensitive
H(1)
H(0)
H(Z)
H(Q)
H(X)
Output driven to V
CC
during bus hold
Output driven to V
SS
during bus hold
Output floats during bus hold
Output remains active during bus hold
Output retains current state during bus hold
R(WH)
R(1)
R(0)
R(Z)
R(Q)
R(X)
Output weakly held at V
CC
during reset
Output driven to V
CC
during reset
Output driven to V
SS
during reset
Output floats during reset
Output remains active during reset
Output retains current state during reset
I(1)
I(0)
I(Z)
I(Q)
I(X)
Output driven to V
CC
during Idle Mode
Output driven to V
SS
during Idle Mode
Output floats during Idle Mode
Output remains active during Idle Mode
Output retains current state during Idle Mode
P(1)
P(0)
P(Z)
P(Q)
P(X)
Output driven to V
CC
during Powerdown Mode
Output driven to V
SS
during Powerdown Mode
Output floats during Powerdown Mode
Output remains active during Powerdown Mode
Output retains current state during Powerdown Mode
9
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