- 您現在的位置：買賣IC網 > PDF目錄365959 > TS80C31X2-ECBB (Atmel Corp.) 8-bit CMOS Microcontroller ROMless PDF資料下載
參數資料
| 型號： | TS80C31X2-ECBB |
| 廠商： | Atmel Corp. |
| 英文描述： | 8-bit CMOS Microcontroller ROMless |
| 中文描述： | 8位CMOS微控制器無ROM |
| 文件頁數： | 19/40頁 |
| 文件大?。?/td> | 484K |
| 代理商： | TS80C31X2-ECBB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Rev. A - Mar. 19, 1999
19
Preliminary
TS80C31X2
Table 7. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 8. IE Register
IE - Interrupt Enable Register (A8h)
7
Reset Value = 0XX0 0000b
Bit addressable
Table 9. IP Register
IPH.x
IP.x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
6
5
4
3
2
1
0
EA
-
-
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Description
7
EA
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2
EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
相關PDF資料 |
PDF描述 |
|---|---|
| TS80C31X2-ECBD | 8-bit CMOS Microcontroller ROMless |
| TS80C31X2-ECBR | 8-bit CMOS Microcontroller ROMless |
| TS80C31X2-ECCB | 8-bit CMOS Microcontroller ROMless |
| TS80C31X2-ECCD | 8-bit CMOS Microcontroller ROMless |
| TS80C31X2-ECCR | 8-bit CMOS Microcontroller ROMless |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TS80C31X2-ECBD | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit CMOS Microcontroller ROMless |
| TS80C31X2-ECBR | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit CMOS Microcontroller ROMless |
| TS80C31X2-ECCB | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit CMOS Microcontroller ROMless |
| TS80C31X2-ECCD | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit CMOS Microcontroller ROMless |
| TS80C31X2-ECCR | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit CMOS Microcontroller ROMless |
發布緊急采購，3分鐘左右您將得到回復。