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參數資料
| 型號： | TS80L188EC13 |
| 元件分類： | 微處理器 |
| 英文描述： | MICROPROCESSOR|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 微處理器| 16位|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數： | 5/57頁 |
| 文件大?。?/td> | 585K |
| 代理商： | TS80L188EC13 |
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80C186EC/188EC, 80L186EC/188EC
272434–2
NOTE:
1. The LC network is only required when using a third overtone crystal.
Figure 2. 80C186EC Clock Connections
80C186EC PERIPHERAL
ARCHITECTURE
The 80C186EC integrates several common system
peripherals with a CPU core to create a compact, yet
powerful system. The integrated peripherals are de-
signed to be flexbile and provide logical interconnec-
tions between supporting units (e.g., the DMA unit
can accept requests from the Serial Communica-
tions Unit).
The list of integrated peripherals includes:
D Two cascaded, 8259A compatible, Programma-
ble Interrupt Controllers
D 3-Channel Timer/Counter Unit
D 2-Channel Serial Communications Unit
D 4-Channel DMA Unit
D 10-Output Chip-Select Unit
D 32-bit Watchdog Timer Unit
D I/O Port Unit
D Refresh Control Unit
D Power Management Unit
The registers associated with each integrated pe-
ripheral are contained within a 128 x 16-bit register
file called the Peripheral Control Block (PCB). The
base address of the PCB is programmable and can
be located on any 256 byte address boundary in ei-
ther memory or I/O space.
Figure 3 provides a list of the registers associated
with the PCB. The Register Bit Summary individually
lists all of the registers and identifies each of their
programming attributes.
5
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